National Semiconductor Corporation

Thanh Lequang

Shaw Wei Lee

Anindya Poddar

Glenn Narvaez

Wayne W Lee

William Jeffery Schaefer

Ram Veeraraghavan

Techniques for improving the manufacture and structure of leadframe chip scale packages and land grid array packages are described. One aspect of the invention pertains to a method for patterning a conductive substrate, which is utilized to form a packaged semiconductor device, wherein a metallic barrier layer and a second metallic layer are utilized as an etching resist. A method, according to another aspect of the invention pertains to covering a metallic barrier layer and second metallic layer with a etch resistant cap such that the etch resistant cap is used as a etching resist. In another aspect of the present invention, a method for treating a conductive leadframe with a CZ treatment is disclosed. In yet another aspect of the present invention, techniques relating to locking grooves within the studs of a studded leadframe are disclosed.

Chip scale and land grid array semiconductor packages

A variety of improved substrate structures and substrate fabrication techniques for use in integrated circuit packaging are described. In one aspect, a substrate strip fabrication technique that facilitates strip testing of the dice mounted thereon is described. The described technique works well even when landings on the substrate are electrolytically plated. In a preferred embodiment, the substrate is formed in a manner that facilitates the use of non-stick detection during wire bonding. In a distinct aspect of the invention the substrate strip has a plurality of distinct molding area tiles that each have a two dimensional array of substrate segments formed thereon. The substrate segments each have a die attach area, a plurality of landing one surface and a plurality of contact pads on the other. The contact pads are positioned substantially across from the landings and are electrically connected thereto by associated vias. The landings have bond pads suitable for use in wire bonding and are preferably arranged in at least one row that extends adjacent or around the die attach area. The contact pads are positioned opposite the landings. With this arrangement, extended routing traces are not required to electrically couple the bond pads to the contact pads.

Substrate strips for use in integrated circuit packaging

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San Jose, CA, United States of America

Thanh Lequang