International Business Machines Corporation

Thamaraiselvan Subramani

Raghu Gaurav GopalaKrishnaSetty

Balaji Upputuri

Aspects of the invention provide for a method of delay defect testing in integrated circuits. In one embodiment, the method includes: generating at least one test pattern based on a transition fault model type; evaluating a dynamic voltage drop for the at least one pattern during a capture cycle and generating a voltage drop value for the at least one test pattern; performing a static timing analysis, using the voltage drop value for the at least one test pattern; evaluating a plurality of paths in the at least one pattern; and masking each path that fails to meet a timing requirement.

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Tamil Nadu, India

Thamaraiselvan Subramani