International Business Machines Corporation

Thamarai Selvi Devarajan

Zhenxing Bi

Donald Francis Canaperi

Balasubramanian Pranatharthiharan

Sanjay C Mehta

Fee Li Lie

Peng Xu

Sivananda K Kanakasabapathy

Muthumanickam Sankarapandian

Kangguo Cheng

Nicolas J Loubet

Soon-Cheon Seo

Eric R Miller

Jingyun Zhang

Hosadurga K Shobha

Chun Wing Yeung

Sean Teehan

Charan V Surisetty

Sagarika Mukesh

Devika Sarkar Grant

Binglin Miao

Aakrati Jain

A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

High aspect ratio buried power rail metallization

A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.

Silicon residue removal in nanosheet transistors

A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures.

Fin type field effect transistors with different pitches and substantially uniform fin reveal

A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins. One or more dielectric layers are formed at a base of the fins and the isolation regions and have a uniform height across the fins and the isolation regions. The uniform height includes a less than 2 nanometer difference across the one or more dielectric layers.

Hybridization fin reveal for uniform fin reveal depth across different fin pitches

A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

Spacer formation on semiconductor device

Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle. The etch cycle comprises performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, and performing a thermal treatment to remove by-products of the etch process. The cyclic etch process can be implemented as part of a replacement metal gate process to remove a dummy gate oxide layer of a dummy gate structure as part of, e.g., a FinFET semiconductor fabrication process flow.

Cyclic etch process to remove dummy gate oxide layer for fin field effect transistor fabrication

A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

A method is presented for forming a semiconductor device. The method includes depositing a sacrificial layer on a fin structure formed on a substrate and then filled with polysilicon, etching a portion of the polysilicon material via a first etching process, and pre-cleaning the surface native oxide layer. The method further includes etching the remaining polysilicon material via a second etching process, and removing polysilicon etch residue formed adjacent the fin structure by a cleaning process. The pre-cleaning is performed by applying ammonia (NH) and nitrogen trifluoride (NF) or by applying buffered hydrofluoric acid (BHF). The first etching process is reactive ion etching (RIE) and the second etching process involves applying nitrogen trifluoride (NF) and hydrogen gas (H).

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Albany, NY, United States of America

Thamarai Selvi Devarajan