Shinko Electric Industries Co., Ltd.

Tetsuya Koyama

Tsuyoshi Kobayashi

Takaharu Yamano

Koichi Tanaka

Hajime Iizuka

Hideaki Sakaguchi

Tadashi Arai

Yuji Kunimoto

Toshio Kobayashi

Kiyoaki Iida

Tomoaki Mashima

Takashi Yanagisawa

Hiroyuki Kato

Nobuyuki Kurashima

Yoshihiro Machida

Masahiro Sunohara

Noriyoshi Shimizu

Akio Rokugawa

Masato Tanaka

Hiromu Arisaka

Hajime Ilzuka

Kosaku Harayama

An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

Electronic part embedded substrate and method of producing an electronic part embedded substrate

Chip embedded substrate and method of producing the same

A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.

Wiring substrate and semiconductor device

An electronic component incorporated substrate includes a first substrate and a second substrate electrically connected to each other by a spacer unit. An electronic component is mounted on the first substrate and arranged between the first substrate and the second substrate. A first encapsulating resin is formed between the first substrate and the second substrate to encapsulate the electronic component. A second encapsulating resin is formed on a first surface of the first encapsulating resin to fill a space between the first encapsulating resin and the second substrate. The spacer unit includes a stacked structure of a first solder ball, a metal post, and a second solder ball stacked in a stacking direction of the first substrate and the second substrate.

Electronic component incorporated substrate and method for manufacturing electronic component incorporated substrate

An electronic component built-in substrate, includes a lower wiring substrate, an electronic component mounted on the lower wiring substrate, an intermediate wiring substrate including an opening portion in which the electronic component is mounted, and arranged in a periphery of the electronic component, and connected to the lower wiring substrate via a first conductive ball, an upper wiring substrate arranged over the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second conductive ball, and a resin filled into respective areas between the lower wiring substrate, the intermediate wiring substrate, and the upper wiring substrate, and sealing the electronic component, wherein the first conductive ball and the second conductive ball are arranged in displaced positions mutually.

Electronic component built-in substrate

A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

A circuit substrate having a mounting surface on which a semiconductor chip is mounted and at least one connection pad formed on the mounting surface is connected to a support plate having at least one mounting portion with a diameter larger than a diameter of the connection pad, through a truncated-cone-shaped solder layer which is formed from at least one solder ball on the basis of a difference between the diameter of the mounting portion and the diameter of the connection pad.

Semiconductor device

First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.

Method of manufacturing a multilayer wiring board

The method for forming wiring includes: laminating a thermosetting resin film and a metallic foil on an insulating substrate where base-layer wiring is formed, a mat surface of the metallic foil facing the resin film, pressing the film and the foil with application of heat; forming an opening in the metallic foil to expose a part of the insulating resin layer in which a via hole is to be formed; forming the via hole in the insulating resin layer by using as a mask the metallic foil; performing a desmear process of the via hole via the opening of the metallic foil; removing the metallic foil; forming an electroless-plated layer that covers the top surface of the insulating resin layer, a side surface of the via hole and a top surface of the base-layer wiring; and forming wiring including an electroplated layer on the electroless-plated layer.

Method for forming wiring on insulating resin layer

A wiring board includes an insulating layer in which a semiconductor chip is embedded, and a wiring structure connected to the semiconductor chip. A reinforcing member reinforcing the insulating layer is embedded in the insulating layer. This enables reduction in a thickness of the wiring board and a suppression of warpage of the wiring board.

Wiring board and method of manufacturing the same

A semiconductor packageis constructed of a semiconductor chip, a sealing resinfor sealing this semiconductor chip, and wiringformed inside the sealing resin. And, the wiringis constructed of pattern wiringconnected to the semiconductor chipand also formed so as to be exposed to a lower surfaceof the sealing resin, and a post partformed so as to extend in a thickness direction of the sealing resin, the post part in which one end is connected to the pattern wiringand also the other end is formed so as to be exposed to an upper surfaceof the sealing resin

Semiconductor package and manufacturing method thereof

It is configured to comprise a semiconductor chip, a resin memberfor forming a cavityin which this semiconductor chipis installed, and wiringconstructed of pattern wiringformed so as to be exposed to an upper surfaceof this resin memberand also connected to the semiconductor chipand a post partin which one end is connected to the pattern wiringand also the other end is formed so as to be exposed to a lower surfaceof the resin member

Growing community of inventors

Nagano, Japan

Tetsuya Koyama