Nec Corporation

Nec C Orporation

Shibaura Institute of Technology

Tetsuya Homma

Mieko Suzuki

Koji Kishimoto

Tatsuya Usami

Akira Kubo

Kazuyoshi Ueno

Kenichi Koyanagi

Hiroki Koga

Takaho Tanigawa

Makoto Sekine

Yukinobu Murao

Tomoyuki Ubusawa

Tomoyuki Furuyama

Akihiro Morikaku

Kumpei Tanaka

A method of recycling useful metals is provided. The method enables useful metals including indium, zinc, yttrium, europium, lanthanum, terbium, gadolinium, antimony, lead, copper, tin, and silver to be recovered from wastes, such as wasted flat panel displays, and recycled economically with small energy consumption. The method of recycling useful metals includes: a step in which wastes comprising various flat panel displays, e.g., liquid-crystal display panels, are crushed/powdered; a step in which the resultant particles are dissolved in an aqueous hydrofluoric acid solution; and a step in which various metal oxides and various metal fluorides which remain undissolved are filtered off and the aqueous hydrofluoric acid solution containing various metal ions is electrolyzed to deposit and recover metals for transparent-electrode oxides, such as indium and zinc, and other useful metals.

Method of recycling useful metal

A fabrication method of a semiconductor device is provided, which enables the formation of a conductive plug in an opening of an interlevel dielectric layer without arising any void. After a first wiring layer is formed on a first interlevel electric layer, a second interlevel dielectric layer is formed on the first interlevel dielectric layer to cover the first wiring layer. A first opening is formed in the second interlevel dielectric layer. A first conductive layer is formed on or over the second interlevel dielectric layer to cover the first opening. A first protection layer is formed on the first conductive layer to cover a first depressed part of the first conductive layer. The first protection layer having a first buried part on the first depressed part. The first protection layer and the first conductive layer are polished by a CMP process until the second interlevel dielectric layer is exposed, thereby selectively leaving the first depressed part within the first opening. The first depressed part left within the first opening constitutes a first conductor plug for electrically interconnecting the first wiring layer with a second wiring layer formed to be contacted with the fist conductor plug.

Fabrication method of semiconductor device

On manufacturing a semiconductor device, preparation is made of an organic layer (101) of a resin which has a relative dielectric constant between 1.8 and 3.5, both inclusive, and which is selected from the group consisting of a polyimide resin and a fluororesin. The organic layer has a slit. A first metal (105) is buried in the slit. A silicon oxide layer (106) containing fluorine is formed on the organic layer so that the silicon oxide layer has a hole on the first metal. A second metal (107) is buried in the hole. Preferably, an additional organic layer (101') of the resin is formed on the silicon oxide layer so that the additional organic layer has an additional slit on the second metal. In this case, a first additional metal (105') is buried in the additional slit. In addition, an additional silicon oxide layer (106') containing fluorine may be formed on the additional organic layer so that the additional silicon oxide layer has an additional hole on the first additional metal. In this event, a second additional metal (107') is buried in the additional hole.

Semiconductor device having an organic resin layer and silicon oxide

A spin on glass composition which includes in a solvent as a main component alkoxysilane represented by H.sub.n Si(OR).sub.4-n, where n is 1, 2, or 3 and R is an alkyl group. Water or alcohol is available as a solvent. It is preferable to add the above alkoxysilane with at least any one of a phosphorus compound, boron compound and a germanium compound. It is also preferable to add the above alkoxysilane not only with tetraalkoxysilane Si(OR).sub.4, where R is an alkyl group, but also with at least any one of phosphorus compound, boron compound and germanium compound.

Spin on glass material and method for forming a semiconductor device by

A method of manufacturing a semiconductor device includes the following steps. A lower wiring layer is formed on a semiconductor substrate through an insulating film. A compound gas having a catalysis for promoting formation of silicon oxide is added in an atmosphere using a main component gas consisting of ozone, water vapor, and one of alkoxysilane and organosiloxane as a source gas to form a silicon oxide film by a chemical vapor deposition (CVD) method directly on a surface of the semiconductor substrate on which the lower wiring layer is formed. An upper wiring layer is formed on the silicon oxide film.

Method of manufacturing semiconductor device

The present invention provides a novel method for forming multilevel interconnections in a semiconductor device. A silicon oxide film is formed on a semiconductor substrate. A first photo-resist film pattern is formed on the first silicon oxide film. The surface of the silicon oxide film covered with the photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a first fluoro-containing silicon oxide film on the silicon oxide film by use of the first photo-resist film pattern as a mask. The first photo-resist film pattern is removed, thereby resulting in first grooves in the fluoro-containing silicon oxide film. First interconnections are formed within the first grooves. An inter-layer insulator is formed on an entire surface of the device and then subjected to a dry etching and a photolithography to form via holes in the inter-layer insulator. Conductive films are selectively formed in the via holes. A second photo-resist film pattern is selectively formed to cover the conductive films within the via holes. The entire surface of the device covered with the second photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a second fluoro-containing silicon oxide film on the inter-layer insulator by use of the second photo-resist film pattern as a mask. The second photo-resist film pattern is removed, thereby resulting in second grooves in the second fluoro-containing silicon oxide film. Second interconnections are formed within the second grooves.

Method for forming multilevel interconnections in a semiconductor device

At least one of an interlayer insulating film is formed by fluorine contained silicon oxynitride which is obtained by chemical deposition growth process using fluoroalkoxysilane gas, nitrogen gas contained gas, and oxygen gas contained gas. The at least one-film is formed at a temperature of lower than 200.degree. C. As a result, reliability of a semiconductor device to be fabricated as described above is enhanced.

Method for fabricating a semiconductor device having multilevel

The invention provides a fabrication method of multilevel interconnections for semiconductor integrated circuits. Aluminium wiring lines are formed on a first silicon oxide film overlying a silicon substrate. A second silicon oxide film is grown by a plasma chemical vapor deposition on the wiring lines and the first silicon oxide film for a specific surface treatment of either an etching with use of fluorine compounds or an ion-implantation of fluorine compounds. A third silicon oxide film is grown on the second silicon oxide film by an atmospheric pressure chemical vapor deposition with use of organic silicon compounds and an oxygen including ozone.

Method of fabricating multilevel interconnections in a semiconductor

The semiconductor device has a multilayer structure wherein a substantially pure silicon dioxide film containing substantially no fluorine atom and a silicon dioxide film containing fluorine atoms are sequentially laminated on a substrate. Etching rate of a silicon dioxide film depends on a fluorine concentration in the film, so that a suitable etch selectivity of the silicon dioxide film containing fluorine atoms from the substantially pure silicon dioxide film can be obtained to form an oxide trench used for a trench interconnection and a via-hole used for a via-plug. The oxide film containing fluorine atoms has as good a quality as the silicon dioxide film not containing impurities has, thereby obtaining a superior characteristic of the semiconductor device. Addition of fluorine atoms reduces a specific permittivity to thereby obtain a higher speed.

Semiconductor device having a silicon oxide film containing fluorine

After forming lower level wiring and plasma oxide layer, SOG film is applied by applying a solution containing hydrogen silsesquioxane as primary component under rotation. Pre-baking of the SOG film is performed by a first heat treatment and causes reflow thereof by a second heat treatment at a temperature higher than the first heat treatment. Subsequently, another plasma oxide layer is formed. By this, in an interlayer insulation layer including SOG film, occurrence of crack and so forth can be prevented and water resistance can be improved.

Fabrication process for multilevel interconnections in a semiconductor

A method which can markedly improve the flatness of a semiconductor integrated circuit device by forming selectively a layer insulating film on an underlying substrate having level differences is disclosed. First, a Ti--W alloy film is formed on a member which brings about level differences due to wirings or the like, then a PECVD silicon oxide film is formed followed by a plasma treatment using CF.sub.4 gas. Further, a silicon oxide film is deposited by atmospheric pressure CVD using ozone and tetraethoxysilane. Then, the surface is flattened by etchback using an organic SOG film, and a silicon oxide film is formed by plasma excited CVD.

Method of producing semiconductor integrated circuit device having

Disclosed herein is abrasives consisting of fine particles of fluorinated silicon oxide which do not contain alkali metal and methods of thier manufacture, and high yield and high reliability methods of manufacturing semiconductor devices by the use of these abrasives. The abrasive comprises a solution in which fine particles of fluorinated silicon oxide are dispersed is formed by addition of boric acid to an aqueous solution of hydrosilicofluoric acid or addition of pure water to an alcohol solution of alkoxyfluorosilane. By the use of these abrasives, a layer insulating film for multi-layer wiring can be flattened.

Method of manufacturing semiconductor device using the abrasive

A spin coated insulating film is coated selectively between wirings by treating the surface of a wiring layer with a fluorine compound gas plasma. The spin on glass film is made compact by exposing it to fluoroalkoxysilane vapor to accelerate condensation and polymerization of the spin coated materials. A silicon oxide film is formed by plasma excited CVD to form a flat interlayer insulating film. A fine mutilayer wiring structure can be readily formed by employing the above mentioned planarizing method of the interlayer insulating film.

Method of fabricating a semiconductor device having a multilayer wiring

A method of manufacturing a semiconductor device, incorporates the steps of: performing reactive ion etching using a fluorine compound gas to surface-treat the lower level wirings which permits selective deposition of the second silicon oxide film; selectively depositing a second silicon oxide film between said lower level wirings by a CVD method using an organic silicon compound gas and an oxidizable gas as source gases; depositing a third silicon oxide film on an entire surface and forming through holes connected to the lower wirings; and forming upper level wirings connected to the lower level wirings. Further, an additional silicon oxide film can be deposited on the major surface so as to form a side wall thereof on the lower level wirings. The reactive ion etching is then performed.

Forming multi-layered interconnections with fluorine compound treatment

In a pattern formation method which employs a resist system of tri-level structure the present method is characterized in that it uses a fluorine contained silicon dioxide film as the intermediate film. Since this fluorine contained silicon dioxide film can be formed at a low temperature with a small volume shrinkage, it is possible to eliminate the generation of cracks and delaminations due to heat treatment. Moreover, it is possible to improve the adhesive strength between an etching object such as a noble metal film and the lower organic film since the lower organic film can be formed by heat treatment at a low temperature.

Growing community of inventors

Tokyo, Japan

Tetsuya Homma