Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Hitachi Vsli Engineering Corp.

Vlsi Engineering Corporation

Tetsurou Matsumoto

Takashi Yamazaki

Kazuyoshi Oshima

Kazuhiko Kajigaya

Masashi Horiguchi

Akira Endo

Ryoichi Hori

Kazuyuki Miyazawa

Jun Etoh

Yuji Sakai

Hiroshi Yoshioka

Yasunori Yamaguchi

Makoto Morino

Yasuhiro Kasama

Shinichi Ikenaga

Shinji Udo

Eiji Miyamoto

Mitsuhiro Takano

Sinichi Miyatake

Manabu Tsunozaki

Jiro Sawada

Atsushi Kumata

Hirokazu Saito

Hiroshi Kikuchi

Asao Nishimura

Kunihiko Nishi

Kunihiro Tsubosaki

Takashi Yokoyama

Gen Murakami

Makoto Kitano

Akihiro Yaguchi

Akio Hasebe

Hiroshi Hozoji

Masahiro Ichitani

Aizo Kaneda

Shozo Nakamura

Junichi Saeki

Isamu Yoshida

Sueo Kawai

Hiroyoshi Kokaku

Noriyuki Kinjo

Masatsugu Ogata

Masanori Segawa

Syuuji Eguchi

Ichiro Anjoh

Yutaka Kobayashi

Kazumasa Yanagisawa

Goro Kitsukawa

Hitoshi Miwa

Atsushi Nozoe

Masayuki Nakamura

Shoji Wada

Tetsu Udagawa

Yoshitaka Kinoshita

Kyoko Ishii

Tatsuyuki Ohta

Hiromi Tsukada

Yoshiaki Ouchi

Kazuo Mihashi

Ichiro Anjo

Akihiro Tamba

Kazuhiko Kazigaya

A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Semiconductor memory device and defect remedying method thereof

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit

Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the 'Lead-On-Chip' or 'Chip-On-Lead' structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Semiconductor device

Growing community of inventors

Higashiyamato, Japan

Tetsurou Matsumoto