Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Tetsuji Nakakuma

Hiroshige Hirano

Nobuyuki Moriwaki

George Nakane

Tatsumi Sumi

Toshio Mukunoki

Takashi Miki

Shunichi Iwanari

Yasuo Murakuki

Masahiko Sakagami

Kunisato Yamaoka

Yasushi Gohou

Toshiyuki Honda

A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Ferroelectric memory and method for reading data from the ferroelectric memory

Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory corestarts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell, in the memory core, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cellor a data write-in to the memory cellis complete, a rewrite timeris activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell

Semiconductor memory device

A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch

To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage areaformed from electrically-rewritable nonvolatile memory and a second setting function storage areaformed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address registerand transfer of operation mode setting information to an operation mode registerare selectively performed.

Semiconductor storage device

Semiconductor device

A reference potential generator is constituted of two signal lines 21 and 22; a charge supplier to supply charge to signal lines 21 and 22; connectors 24a and 24b connecting the charge supplier 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a connector 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, '1' or '0' of readout data can be precisely determined.

Reference potential generator and a semiconductor memory device having

A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, '1' or '0' of readout data can be precisely determined.

A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying means to supply charge to signal lines 21 and 22; a first connection circuit 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, '1' or '0' of readout data can be precisely determined.

In an electric signal supply circuit, a signal generating source and a plurality of circuit cells are connected to each other by a wire line through resistors. Signal wire lines from the signal generating source to the respective circuit cells are formed in the form of a pyramid, and therefore, delay time differences to the circuit cells are reduced. Since delay time differences in a signal to the circuit cells from the signal generating source which is disposed at ends of the plurality of circuit cells are smaller, a circuit operation is stable.

Electric signal supply circuit and semiconductor memory device

A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.

Ferroelectric memory devices and method for testing them

The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value '1.' This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.

Semiconductor memory device including reverse and rewrite means

A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.

Semiconductor memory device with redundant memory cell backup

A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.

Growing community of inventors

Shiga, Japan

Tetsuji Nakakuma