Other

Hitachi, Ltd.

Teruaki Kisu

Kazuo Nakazato

Masahito Takahashi

Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n type semiconductor regions via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.

Growing community of inventors

Tokyo, Japan

Teruaki Kisu