Applied Materials, Inc.

Other

Terry Leung

Chang-Lin Hsieh

Yan Ye

Michael D Armacost

Jie Yuan

Yifeng Zhou

Siyi Li

Silvia Halim

Qiqun Zheng

Takehiko Komatsu

QiQun Zhang

A substrate comprising a resist layer overlying a dielectric feature, is processed in a substrate processing chamber comprising an antenna, and first and second process electrodes. A process gas comprising COis introduced into the chamber. The process gas is energized to form a plasma by applying a source voltage to the antenna, and by applying to the electrodes, a first bias voltage having a first frequency of at least about 10 MHz and a second bias voltage having a second frequency of less than about 4 MHz. The ratio of the power level of the first bias voltage to the second bias voltage is sufficient to obtain an edge facet height of the underlying dielectric feature that is at least about 10% of the height of the dielectric feature.

Plasma for resist removal and facet control of underlying features

Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating ('BARC') is commonly deposited into the via and field regions surrounding the via,. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC,, surrounded by 'fencing' material,, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARC plug,, partially filling the via and having a convex upper surface,, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating. A directional, anisotropic etching of BARC, and more particularly, an ammonia plasma etch, is one convenient method of removing BARC and forming the desired convex upper surface.

BARC shaping for improved fabrication of dual damascene integrated circuit features

The present invention provides a low-k dielectric etching process with high etching selectivities with respect to adjacent layers of other materials, such as an overlying photoresist mask and an underlying barrier/liner layer. The process comprises the step of exposing a portion of the low-k dielectric layer to a plasma of a process gas that includes a fluorocarbon gas, a nitrogen-containing gas, and an inert gas, wherein the volumetric flow ratio of inert:fluorocarbon gas is in the range of 20:1 to 100:1, and the volumetric flow ratio of fluorocarbon:nitrogen-containing gas is selected to provide a low-k dielectric to photoresist etching selectivity ratio greater than about 5:1 and a low-k dielectric etch rate higher than about 4000 &#x212b;/min.

Selective etching of low-k dielectrics

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San Jose, CA, United States of America

Terry Leung