United Microelectronics Corp.

United Silicon Incorporated

Terry Chung-Yi Chen

Tong-Hsin Lee

Cheng-Chih Kung

Cheng-Chieh Huang

Da-Wen Hsia

A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5&times;10 &tilde;5&times;10 cm and at an implantation energy level between 2 KeV&tilde;5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.

Method of manufacturing MOS transistor with fluoride implantation on silicon nitride etching stop layer

Method of manufacturing MOS transistor with fluorine implantation at a low energy

A fabrication method of a node contact opening involves forming a first insulating layer on the substrate, in which a bit line, which contacts the substrate, is formed on the first insulating layer. A conformal second insulating layer that serves as an etching stop layer is formed after the formation of bit line. A third insulating layer is then formed to isolate the subsequently formed capacitor and bit line. A pattern mask is formed on the third insulating layer, while a pattern of the pattern mask is transferred into the third insulating layer, so that an opening is formed in the third insulating layer. After the second insulating layer in the opening is removed, a spacer is formed on a sidewall of the opening. With the pattern mask and the spacer serving as an etching mask, the first insulating layer below the bit line is etched until the opening is extended through to the substrate, so that a contact opening is formed.

Method of fabricating node contact opening

A method of fabricating a self-aligned storage node is described. A storage node plug is formed after formations of the bit line contact and the storage node contact. A spacer is formed on a sidewall of an opening, which is used for forming a bit line. The bit line is formed in the opening. Because the spacer provides good isolation, the tolerance window for forming the bit line is increased. Some follow-up steps are performed to form a storage node.

Method of fabricating self-aligned node

A fabrication method for a copper (Cu) damascene, involving etching a part of a dielectric layer after formation of the Cu conducting wires, so that the Cu conducting wires project out from the surface of the dielectric layer. A top barrier layer is formed to prevent Cu electromigration (EM) and current leakage.

Method of fabricating copper damascene

A method for forming a capacitor containing selective hemispherical grained (S-HSG) polysilicon is disclosed. In this invention, dopant implantation is incorporated after the S-HSG growth to replace conventional wet clean procedure. The elimination of the cleaning treatments avoids the incidents of residue particles (due to cleaning) and minimizes numerous structure defects. The incorporation of the ion implantation technique would make up the insufficiency of doping requirement by applying in-diffusion alone. The combination of the in-diffusion and the implantation for doping procedure could maintain the device with good capacitance level even though the pre-clean procedure is excluded.

Method for forming a capacitor having selective hemispherical grained polysilicon

A method of fabricating a dynamic random-access memory (DRAM) device integrates a shallow trench isolation (STI) process and a storage node process into the fabrication of the DRAM device. With a bit line over capacitor (BOC) structure, the capacitor is laid out in parts of the shallow trench isolation structure to increase the surface area of the storage node by using the trench. During the fabrication of the capacitor, a stacked plug used to connect the bit line is formed. The stacked plug used as the interconnection in the circuit region is also formed. An insulating layer is formed to cover the capacitor, and an opening is formed therein to expose the stacked plug. A bit line and an interconnection are formed on the insulating layer to connect with a conducting layer which is located in the stacked plug and contacted with the source/drain regions.

Growing community of inventors

Taipei Hsien, Taiwan

Terry Chung-Yi Chen