Advanced Semiconductor Engineering, Inc.

Te Tsung Chao

Hui Chin Fang

Yung I Yeh

Ya Ping Hung

A method of automatic identifying and skipping defective work pieces mainly utilizes a reject eye formed inside the die covering area on a substrate to automatically determine whether the skipping procedure is triggered or not. The method of the present invention comprises the steps of: finding and aligning the die eye of the die as well as the lead eye of the substrate; finding the reject eye when the die eye and the lead eye is evaluated as not being present; stopping the wire bonding operation and skipping to next work piece when the reject eye is located. The method of present invention is capable of automatically determining whether the skipping procedure is triggered or not thereby reducing operating down time and increasing throughput.

Method of automatically identifying and skipping defective work pieces for wire-bonding operation

A method for positioning bond pads in a semiconductor die comprises the steps of (I) setting parameters including (a) setting a baseline pad pitch to a first value, (b) setting a first pad position equal to a first pad value and (c) providing a focal point; (II) determining a first angle between a first line through a center of the first pad position and the focal point and a second line through a center of the semiconductor die and normal to the edge; (III) determining a first pad spacing increment value equal to the first value divided by a cosine of the first angle; (IV) setting a second pad position equal to a second pad value, wherein the second pad value at least equals the first pad value plus the first value if both of the first bond pad and the second bond pad are ground pad or power pad with the same potential, else the second pad value at least equals the first pad value plus the first pad spacing increment value; and (V) using the first and second pad values to respectively position a first bond pad and a second bond pad along the edge of the semiconductor die. Beginning from the bond pad closest to the die corner, optimized positions of bond pads can be determined by repeating steps I to V.

Method for positioning bond pads in a semiconductor die

A BGA package includes a chip with an array pad design disposed on the upper surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof, and the bonding pads of the chip are positioned in three rows, an inner row, a middle row, and an outer row along the sides of the chip. Only power supply pads and ground pads are designed to be located in the outer row of bonding pads, and all of the I/O pads are designed to be located in the middle row of the bonding pads and the inner row of the bonding pads. The outer row, middle row, and the inner row of the bonding pads are electrically connected to the substrate through three tiers of bonding wires with different loop height, respectively,

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Kaohsiung, Taiwan

Te Tsung Chao