United Microelectronics Corp.

Te-Sheng Yang

Kai-Kuang Ho

Charlie Han

This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and takes advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids that would form unbalanceable thermal mold flow. The heat sink can also dissipate heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and can increase the quality of integrated circuits.

Integrated circuit packages and the method for making the same

This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and take advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids form unbalanceable thermal mold flow. The heat sink can also dissipating heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and increasing the qualities in integrated circuits.

Integrated circuit packages and the method for the same

A dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes an upper surface and a lower surface. A first die, having several first bonding pads, is fixed on the upper surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the lower surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other.

Dual-dies packaging structure and packaging method

A dual silicon chip package structure is described, whose first silicon chip is supported by special lead frame pins. The lead frame pins extend into the peripheral region of the first silicon chip so that the front surface of the first silicon chip can be attached to those lead frame pins. Bonding pads on the front surface of the first silicon chip are located around the central region. The backside of a second silicon chip is attached to the backside of the first silicon chip. Bonding pads on both the first silicon chip and the second silicon chip are connected to the lead frame using conductive wires. In addition, if the second silicon chip is smaller than the first silicon chip, the second silicon chip can sit with its backside on top of the front surface of the first silicon chip as well. In that case, the backside of the first silicon chip has to sit above the lead frame pins, and the bonding pads on the front surface of the first silicon chip has to be located around the peripheral region.

Dual silicon chip package

A wafer-level chip scale package. The structure is applicable in packing at least two dies into a same package. The volume of the package is approximately equal to the total volume of the packed dies. A first die is provided. A pad redistribution step is performed on the first chip. Using flip chip technique, a second die is connected onto the first die. The first die has a surface area larger than that of the second die. Using a molding process, a molding material is infilled into spaces between the first and the second die. In addition, bumps are formed on the first chip with one ends thereof exposed and the other part covered by the molding material. Solder balls are formed on the exposed end of the bumps as terminals to electrically connect an external circuit or device.

Wafer-level chip scale package

A method of fabricating wafer-level package. The package is applicable in packing at least two dies. The volume of the package is approximately equal to the total volume of the packed dies. A first die is provided. A pad redistribution step is performed on the first die. After performing a pad redistribution step on the first die, an insulator is formed on a peripheral region over the first die. The insulator prevents from contaminating a central region circumscribed by the insulator over the first die during the subsequent molding or coating step. The first die is adhered onto a second die with an insulating tape or non-conductive glue. Using a bonding technique, metal wires are bonded to connect the first die and the second die, so as to transmit the signal and conduct the electricity between the first and the second dies. Using molding or coating, the metal wires are fixed and protected. Soldering balls are formed on the central region over the first die to provide terminals for connecting an external device or circuit.

Growing community of inventors

Taiipei, Taiwan

Te-Sheng Yang