Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Te-Hsien Hsieh

Jing-Yi Lee

Ming-Jui Chen

Cheng-Te Wang

Shih-Ming Kuo

Yuan-Tai Tseng

Lee-Chuan Tseng

Ping-I Hsieh

Kuo-Chi Tu

Tzu-Yu Chen

Yu-Hsing Chang

Yi-Min Chen

Yan-Chun Chen

Yung-Chang Chang

Shih-Wei Lin

Jung-I Lin

Jian-Yuan Ma

In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

Via landing on first and second barrier layers to reduce cleaning time of conductive structure

In some embodiments, the present disclosure relates to a method of performing an etching process. The method includes generating a plasma within a plasma chamber in communication with a processing chamber. Ions from the plasma are accelerated toward a workpiece within the processing chamber to generate an ion beam. The ion beam performs an etching process that etches a material on the workpiece. A by-product from the etching process is moved to directly below one or more baffles within the processing chamber.

Ion beam etching chamber with etching by-product redistributor

In some embodiments, the present disclosure relates to an etching apparatus. The etching apparatus includes a substrate holder disposed within a processing chamber and having a workpiece reception surface configured to hold a workpiece. A lower surface of the processing chamber has a first region that is directly below the workpiece reception surface and that is configured to receive a byproduct from an etching process. A baffle extends outward from a sidewall of the processing chamber at a vertical position between the substrate holder and the lower surface of the processing chamber. The baffle covers a second region of the lower surface. A byproduct redistributor is configured to move the byproduct from the first region of the lower surface to the second region of the lower surface that is directly below the baffle.

The present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material region. A second semiconductor material region is disposed onto the substrate. A patterned doped layer is arranged between the substrate and the second semiconductor material region. The second semiconductor material region includes a sidewall connecting to a bottom surface of the second semiconductor material region. The sidewall extends through the patterned doped layer. A bottom surface of the second semiconductor material region is directly over the photodiode region.

Channel pattern design to improve carrier transfer efficiency

An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.

3D RRAM cell structure for reducing forming and set voltages

A memory device including a first array of rail structures that extend along a first horizontal direction, in which each of the rail structures are formed to serve as a bottom electrode, and a second array of rail structures that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction. Each of the rail structures in the second array are formed to server as a top electrode. The memory device also includes a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures. The continuous dielectric memory layer providing protection from current leakage between the rail structures of the first array and the rail structures of the second array.

High density memory devices with low cell leakage and methods for forming the same

In some embodiments, the present disclosure relates to an ion beam etching apparatus. The ion beam etching apparatus includes a substrate holder disposed within a processing chamber and a plasma source in communication with the processing chamber. A vacuum pump is coupled to the processing chamber by way of an inlet. One or more baffles are arranged between the substrate holder and a lower surface of the processing chamber. A by-product redistributor is configured to move a by-product from an etching process from outside of the one or more baffles to directly below the one or more baffles.

The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.

Pattern verifying method

A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

Method for optimizing an integrated circuit layout design

A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.

Method and apparatus for integrated circuit design

A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments.

Method of optical proximity correction

A mask pattern and a correcting method thereof are provided. The correcting method includes the following steps. An original pattern having a first original contour and a second original contour is provided. The first original contour has a first original corner. The second original contour has a second original corner, which is near the first original corner. The first and second original corners are cut to form a cut pattern. An optical proximity correction (OPC) process is applied to the cut pattern to form the mask pattern.

Mask pattern and correcting method thereof

A method of optical proximity correction (OPC) includes the following steps. At first, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into at least a first region and at least a second region. Then, several iterations of OPC calculations are performed to the layout pattern, and a total number of OPC calculations performed in the first region is substantially larger than a total number of OPC calculations performed in the second region. Afterwards, a corrected layout pattern is outputted through the computer system onto a mask.

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Kaohsiung, Taiwan

Te-Hsien Hsieh