Advanced Micro Devices Corporation

Fasl LLC

Other

Spansion Llc.

Cypress Semiconductor Corporation

Tazrien Kamal

Mark T Ramsbey

Hidehiko Shiraiwa

Jean Y Yang

Arvind Halliyal

Minh Van Ngo

Jaeyong Park

Emmanuil Lingunis

Rinji Sugino

Angela Tai Hui

Weidong Qian

Jeffrey Allan Shields

Wei Zheng

Kouros Ghandehari

Amir Hossein Jafarpour

Mark W Randolph

Ning Cheng

Jean Yee-Mei Yang

Jeff P Erhardt

Fred T K Cheung

Hiroyuki Kinoshita

Dawn M Hopper

Yi He

Robert A Huertas

Inkuk Kang

Pei-Yuan Gao

Tyagamohan Gottipati

Scott Allan Bell

Chi K Chang

Cyrus E Tabery

Yider Wu

Kashmir S Sahota

Michael A VanBuskirk

David Michael Rogers

Yun Wu

Mimi Xuefeng Qian

Clarence B Ferguson

Taraneh Jamali-Beh

Kwadwo A Appiah

Sameer S Haddad

Yu Nan Sun

Cinti Xiaohua Chen

Edward Hsia

Jusuke Ogura

Nga-Ching Wong

Ashok M Khathuria

Pei Yuan Gao

Jeyong Park

Emmanuil Manos Lingunis

A semiconductor device () for improved charge dissipation protection includes a substrate (), a layer of semiconductive or conductive material (), one or more thin film devices () and a charge passage device (). The thin film devices () are connected to the semiconductive or conductive layer () and the charge passage device () is coupled to the thin film devices () and to the substrate () and provides a connection from the thin film devices () to the substrate () to dissipate charge from the semiconductive/conductive layer () to the substrate ().

Method and apparatus for protection against process-induced charging

A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.

Memory manufacturing process with bitline isolation

A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.

Method for forming bit lines for semiconductor devices

A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.

A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.

Semiconductor memory with data retention liner

The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or 'packed' within the same or a smaller area.

LDC implant for mirrorbit to improve Vt roll-off and form sharper junction

The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.

Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device

A Si-rich silicon oxide layer having reduced UV transmission is deposited by PECVD, on an interlayer dielectric, prior to metallization, thereby reducing V. Embodiments include depositing a UV opaque Si-rich silicon oxide layer having an R.I. of 1.7 to 2.0.

PECVD silicon-rich oxide layer for reduced UV charging

A memory includes a semiconductor substrate and a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited and formed. A doped wordline spacer layer is deposited and a doped wordline spacer is formed adjacent to the wordline.

Memory wordline spacer

Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silicon interface; treating the bottom oxide layer to increase the first oxygen content to a second oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer. In another embodiment, process for reducing charge leakage in a SONOS flash memory device, including forming a bottom oxide layer of an ONO structure on a surface of the semiconductor substrate having an oxide/silicon interface with a super-stoichiometric oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer.

ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices

Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 &#x212b; to 600 &#x212b;, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

Undoped oxide liner/BPSG for improved data retention

The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.

Disposable hard mask for memory bitline scaling

A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing

A non-volatile memory device includes a semiconductor substrate and an N-type source and drain within the substrate. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a thin bottom oxide layer. A Ppolysilicon gate electrode is formed over the ONO stack. The memory device is operative to perform a channel erase operation in which a pair of charge storing cells within the nitride layer are erased simultaneously.

Memory device having a P+ gate and thin bottom oxide and method of erasing same

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San Jose, CA, United States of America

Tazrien Kamal