Texas Instruments Corporation

Taylor R Efland

Sameer P Pendharkar

Chin-Yu Tsai

Dale J Skelton

Satwinder S Malhi

Marie Denison

Charles E Williams

Oh-Kyong Kwon

Alec James Morton

Quang X Mai

Ramanathan Ramani

Wai Tung Ng

Michael C Smayling

Ross Eliot Teggatz

Louis N Hutter

Jozef C Mitros

Joseph A Devore

David Alexander Grant

John P Erdeljac

Dan M Mosher

Binghua Hu

Philip Leland Hower

Roy Clifton Jones, Iii

Stephen C Kwan

David D Briggs

David R Cotton

Milton Lee Buschbom

Dave Cotton

Sridhar Seetharaman

Christopher Boguslaw Kocon

Marco Corsi

Donald Charles Abbott

Imran Khan

Chi-Cheong Shen

Stephen A Keller

Konrad Wagensohner

Jeffrey P Smith

Kenneth G Buss

Walter Bucksch

Mark Stephen Rodder

Sreenivasan Kalyani Koduri

Henry Litzmann Edwards

Amitava Chatterjee

Wayne T Chen

Steven Alfred Kummerl

Han-Tzong Yuan

James Robert Todd

Tathagata Chatterjee

Keith Edmund Kunz

John Lin

Joe R Trogolo

Michael G Amaro

Jau-Yuann Yang

James R Hellums

Thomas A Schmidt

Lester L Hodson

John Kenneth Arch

Buford H Carter, Jr

Steven C Jones

Vladimir Bolkhovsky

William E Nehrer

C Matthew Thompson

Mary Ann Murphy

R Travis Summerlin

Chao-Chih Chiu

John K Lee

Sam Shichijo

Peter Chia-cu Mei

A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.

Power integrated circuit including series-connected source substrate and drain substrate power mosfets

Power integrated circuit including series-connected source substrate and drain substrate power MOSFETs

A pallet () supporting a half-etched leadframe with cantilever-type leads () without metallic supports during the step of attaching components () to the leads in order to assemble an electronic system. After assembly, the pallet is removed before the molding step that encapsulates () the components on the leadframe and mechanically supports () the cantilever leads. The pallet is machined from metal or inert plastic material, tolerates elevated temperatures during soldering, and is reusable for the next assembly batch.

Multi-component electronic system having leadframe with support-free with cantilever leads

An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

MOS transistor with gate trench adjacent to drain extension field insulation

An integrated circuit () includes one of more transistors () on or in a substrate () having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (). The DEMOS transistor includes a drift region () in the surface layer having a first dopant type, a field dielectric () in or on a portion of the surface layer, and a body region of a second dopant type () within the drift region (). The body region () has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric () is on at least a portion of the body wall. An electrically conductive gate electrode () is on the gate dielectric () on the body wall. A source region () of the first doping type is in the body region (), a drain region () of the first doping type is in the drift region (), and interconnects () are operable to electrically connect the one or more transistors to each other on the integrated circuit ().

Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric

An integrated circuit () includes one of more transistors () on or in a substrate () having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (). The DEMOS transistor includes a drift region () in the surface layer having a first dopant type, a field dielectric () in or on a portion of said surface layer, and a body region of a second dopant type () within the drift region (). The body region () has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric () is on at least a portion of the body wall. An electrically conductive gate electrode () is on the gate dielectric () on the body wall. A source region () of the first doping type is in the body region (), a drain region () of the first doping type is in the drift region (), and interconnects () are operable to electrically connect the one or more transistors to each other on the integrated circuit ().

An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 m&#x3a9;/&#xb7; and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

Individualized low parasitic power distribution lines deposited over active integrated circuits

Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

Robust DEMOS transistors and method for making the same

An improved n-channel integrated lateral DMOS () in which a buried body region (), beneath and self-aligned to the source () and normal body diffusions, provides a low impedance path for holes emitted at the drain region (). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.

N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects

The concept of the present invention describes a semiconductor device with a junctionbetween a lightly doped regionand a heavily doped region, wherein the junction has an elongated portionand curved portions. The doping concentration of the lightly doped region is configured so that it exhibits higher resistivity in the proximityof the curved portion by an amount suitable to lower the electric field strength during device operation and thus to offset the increased field strength caused by the curved portion. As a consequence, the device breakdown voltage in the curved junction portion becomes equal to or greater than the breakdown voltage in the linear portion.

Premature breakdown in submicron device geometries

An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 m&#x3a9;/&#x25a1; and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. The network relocates most of the conventional power distribution interconnections from the circuit level to the newly created surface network, thus saving substantial amounts of silicon real estate and permitting shrinkage of the IC area. The network is electrically connected to selected active components by metal-filled vias; since these vias can easily be redesigned to other locations, IC designers gain a new degree of design freedom. The network relocates most of the bond pads dedicated to power supply from the conventional alignment along the chip periphery onto the newly created bondable lines, saving substantial additional amounts of silicon real estate, and freeing the bonding machines from their extremely tight connector placement and attachment rules to much more relaxed bonding programs. The network is deposited and patterned in wafer processing as a sequence of metal layers specifically suited for providing power current and electrical ground potential. The network has attachable outermost metal surface and is laid out so that network portions form pads convenient for attaching balls of bonding wires or solder.

Circuit method integrating the power distribution functions of the circuits and leadframes into the chip surface

Growing community of inventors

Richardson, TX, United States of America

Taylor R Efland