Kabushiki Kaisha Toshiba

Tatsuro Mitani

Yoshihiro Kishita

Motoki Furukawa

Kazuhiko Inoue

Kazuo Endo

Toshikazu Fukuda

Tetsuo Ishii

Noboru Noda

A semiconductor layer undergoes isolation etching and gate recess etching, using a side wall insulating layer having the shape of a forward taper as a mask, by means of the anisotropic etching technique. The shape of the side wall of the semiconductor layer corresponds to that of the forward taper of the mask. The shape of the forward taper is always constant, irrespective of face orientation of crystal of the semiconductor layer. Since the taper angle of the side wall insulating layer can freely be set within a predetermined range in accordance with conditions, the taper angle of the semiconductor layer can be controlled. The design margin of an electrode wiring pattern is greatly improved. Since the side wall of a gate recess is stably formed in the shape of a forward taper, the side wall insulating layer can be formed on the surface of the forward taper and thus a gate electrode layer can be formed so as to have a T-shaped cross section. Therefore, the gate resistance can be greatly reduced.

Method of manufacturing a semiconductor device

A semiconductor device comprising a compound semiconductor substrate whose surface is provided with a source region, a drain region and an interventing channel region; a source electrode formed on said source region; a drain electrode mounted on said drain region; and a 3-ply gate electrode formed on said channel region and consisting of a high melting metal layer, a barrier metal layer and a gold layer in that order.

Semiconductor device with a 3-ply gate electrode

A gate structure of a MOS FET has an oxide layer and an electrode layer sequentially formed on a silicon substrate. In the gate structure, the electrode layer includes a first silicidized high-melting metal layer formed on the oxide layer, a high-melting metal layer formed on the first silicidized high-melting metal layer and a second silicidized high-melting metal layer formed on the high-melting metal layer.

Gate structure for a MOS FET

Disclosed is a semiconductor device with its gate electrode and source/drain extraction electrodes being made of the same material on a GaAs substrate, and with its source/drain heavily doped regions, which are formed by doping Se in a lightly doped semiconductor layer on the GaAs substrate, self-aligned with both gate electrode and source/drain extraction electrodes.

Method for manufacturing semiconductor device

A GaAs semiconductor device, includes a p-type GaAs substrate, an n-type region formed in the surface area of the substrate, an ohmic contact electrode formed in ohmic contact with the n.sup.+ -type region and having a layer of alloy of gold, and an interconnection electrode formed on the ohmic contact electrode and including an upper layer of aluminum and a lower layer of a metal which prevents gold from passing through it. The interconnection electrode is formed such that it covers the top and side surfaces of the ohmic contact electrode.

GAAS semiconductor device

Disclosed is a method for forming a conductor pattern which comprises the steps of forming a conductive layer on a semiconductor substrate, forming a photoresist film on the conductive layer, removing that portion of the photoresist film located on a conductor pattern forming region of the conductive layer, forming a first masking metal film over the whole surface of the resultant structure, removing the photoresist film along with that portion of the first masking metal film formed thereon so that a portion of the first masking film remains on the conductor pattern forming region of the conductive layer to form a first masking metal pattern, and selectively removing the conductive layer by anisotropic etching to form the conductor pattern. Since the selective removal of the conductor layer is accomplished by the use of the metal pattern as a mask, it is possible to form a much finer conductor pattern than is obtained with the use of the photoresist pattern as the mask.

Method for forming a conductor pattern using lift-off

A method of forming an electrode pattern on a surface of a semiconductor substrate which comprises the steps of forming a metal film which is vulnerable to a reactive ion etching on a surface of the semiconductor substrate, forming on the metal film another metal film which is vulnerable to an ion milling but is resistant to the reactive ion etching, forming a resist pattern on the another metal film, selectively etching the another metal film by the ion milling using the resist pattern as a mask, and selectively etching the metal film by the reactive ion etching using the another metal film as a mask. A semiconductor device having an electrode pattern as formed by the above method is also disclosed.

Method of forming electrode pattern of semiconductor device

A method for manufacturing semiconductor devices is presented. The method comprises the steps of opening two windows on an insulating layer covering a semiconductor substrate, and forming a polysilicon layer over the entire surface of the insulating layer and the windows. Donor and acceptor impurities are respectively implanted into the portions of the polysilicon layer corresponding to the two opening windows through the appropriate photoresists. The doped impurities are thereafter subjected to annealing to form two different conduction type regions under the two opening windows. Thereafter, a metal layer and a photoresist are deposited in order to make the metal electrodes for each conduction region. Thus, the patterning of the polysilicon can be made in self-alignment with the etching mask, and the formation of two different conduction type semiconductor regions are simultaneously attained.

Growing community of inventors

Tokyo, Japan

Tatsuro Mitani