Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Tatsuo Sugiyama

Noboru Nomura

Tokuhiko Tamaki

Hiroaki Nakaoka

Shinichi Ogawa

Satoshi Ueda

Kousaku Yano

Junji Hirase

Satoshi Shibata

Michikazu Matsumoto

Masahiro Yasumi

Yasushi Naito

Mitsuru Sekiguchi

Shuji Hirao

Fumitoshi Kawase

Masato Kanazawa

Kikuko Nakamura

Kikuko Tsutsumi

Kouji Tamura

Kousaka Yano

Emi Kanasaki

When the emissivity &#x3b5; on the reverse face of a substrateis measured during annealing processing for the substratefilms made from a material that varies the emissivity &#x3b5;, such as a first DPS filmused for forming a plugA, a second DPS filmused for forming a capacitor lower electrodeA and a third DPS filmused for forming a capacitor upper electrodeA, are formed on the top face of the substrateOn the other hand, no film made from a material that varies the emissivity &#x3b5;, such as a DPS film, is formed on the reverse face of the substrate

Method for measuring temperature, annealing method and method for fabricating semiconductor device

While conventionally, a Co film is deposited by directional sputtering directly on a source/drain diffusion layer formed on the surface of an Si substrate while the substrate is being heated, a thin oxide film is formed on the source/drain diffusion layer and then, the Co film is deposited by directional sputtering while the substrate is being heated. By doing this, an inner Co&mdash;Si layer the composition of which is thermally unstable is formed and a Co&mdash;Si&mdash;O layer is formed on the Co&mdash;Si layer. After the remaining unreacted Co film and the Co&mdash;Si&mdash;O layer are selectively removed, a high-temperature heat treatment is performed, so that the inner Co&mdash;Si layer is transformed into a CoSi layer to increase the film thickness. The formation of the oxide film curbs the speed of reaction between Co and Si, so that a Co&mdash;Si layer of the same thickness as that in the wide region can be formed in the fine region. As a result, a CoSi layer with uniform thickness and sheet resistance can be formed.

Method of manufacturing a semiconductor device

A method for fabricating a semiconductor device including a silicon region and a cobalt silicide film, the cobalt silicide film being in contact with at least a part of the silicon region. The method includes the steps of: doping at least part of the silicon region with boron by setting a doping level of boron in the part at 1.times.10.sup.15 cm.sup.-3 or more; depositing a cobalt film over a surface of the silicon region; conducting a first heat treatment for producing a silicidation reaction in a contact region between the cobalt film and the silicon region and thereby forming the cobalt silicide film; selectively removing unreacted portions of the cobalt film that have not been turned into silicide; and conducting a second heat treatment at a temperature higher than a temperature set for the first heat treatment step, thereby inducing a phase transition in the cobalt silicide film. The first heat treatment step is performed within a reducing ambient gas, and the temperature set for the first heat treatment step is in the range from about 400.degree. C. to about 600.degree. C., both inclusive.

Method for fabricating semiconductor device

After forming a polysilicon film to be used as a gate electrode on a semiconductor substrate of silicon, an insulating thin film is deposited on the polysilicon film. Impurity ions are implanted into the polysilicon film through the insulating thin film, so as to form an amorphous layer on the surface of the polysilicon film. After removing the insulating thin film existing on the polysilicon film, a metal film is deposited on the amorphous layer. A reaction is caused between the amorphous layer and the metal film through annealing, so as to form a metal silicide layer on the surface of the polysilicon film.

Method of manufacturing semiconductor device

A first metallization layer is locally formed on the surface of a semiconductor substrate thereby leaving portions of the semiconductor substrate's surface exposed. A first silicon oxide layer is then formed in such a manner that it covers the exposed portions of the semiconductor substrate's surface and the first metallization layer. This is followed by the formation of an HMDS molecular layer on the first silicon oxide layer. Then, a second silicon oxide is formed on the molecular layer by means of a CVD process utilizing the chemical reaction of ozone with TEOS. Finally, a second metallization layer is locally formed on the second silicon oxide layer.

Method for manufacturing a semiconductor device involving forming two

On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon semiconductor layers, laterally paired second p-type silicon semiconductor layers, and laterally paired n-type silicon semiconductor layers, by an epitaxial growth method. On the second n-type silicon semiconductor layer on the right side, there are successively formed a third p-type silicon semiconductor layer, a third n-type silicon semiconductor layer and a fourth p-type silicon semiconductor layer. The left first n-type silicon semiconductor layer, left second p-type silicon semiconductor layer and left second n-type silicon semiconductor layer form a first insular multilayered portion forming an n-channel MOSFET. The third p-type silicon semiconductor layer, third n-type silicon semiconductor layer and fourth p-type silicon semiconductor layer form a second insular portion forming a p-channel MOSFET. A first gate electrode is formed on a side surface of the left second p-type silicon semiconductor layer with a gate insulating film therebetween, and a second gate electrode is formed on a side surface of the right third n-type silicon semiconductor layer with a gate insulating film therebetween.

Semiconductor device with a vertical field effect transistor and method

A first electrode and a first insulating layer of electrode insulation are formed on a first semiconductor substrate. A second electrode and a second insulating layer of electrode insulation are formed on a second semiconductor substrate. The first semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement. Likewise, the second semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement, wherein the pattern of the second semiconductor substrate has a phase shift of 180 degrees with respect to the pattern of the first semiconductor substrate. The first and second semiconductor substrates are bonded together with their patterns in engagement.

Semiconductor device and associated fabrication method

Semiconductor device and method of manufacturing the same

Semiconductor device with a vertical field effect transistor

Growing community of inventors

Osaka, Japan

Tatsuo Sugiyama