Sharp Kabushiki Kaisha Corporation

Sharp Microelectronics Technology, Inc.

Implanted Material Technology, Inc.

Tatsuo Nakato

David A Vidusek

Narayanan Meyyappan

Sheng Teng Hsu

A method for fabricating a GeSi/Si/SiO.sub.2 heterostructure comprises the steps of: (a) providing a monocrystalline Si substrate; (b) defining a GeSi region within the Si substrate while leaving a Si cap overlying the GeSi region, the Si cap being an integral part of the monocrystalline substrate; and (c) oxidizing part of the Si cap to thereby produce the GeSi/Si/SiO.sub.2 heterostructure.

Method for forming silicon-germanium/Si/silicon dioxide heterostructure

A planarizing technique comprising: coating a topography overlying a substrate with a planarizing resist layer; softbaking the planarizing resist layer in the presence of a silicon-containing vapor or liquid; coating the planarizing resist layer with an imaging resist layer; softbaking the imaging resist; selectively exposing the imaging resist layer to light; developing the imaging resist layer; and etching the planarizing layer. The planarizing layer may comprise novolacs and other organic polymers used conventionally in lithographic processes. The planarizing layer may further comprise any organic acid moiety that is compatible with the solvent used to dissolve the resin. In particular, the acid moiety is indole-3-carboxylic acid. In another aspect, the invention comprises a silylated planarizing resist. The resist comprises: a solution of a polymer and an acid, the polymer being selected from the group consisting of a novolac, polymethylmethacrylate, polyhydroxystyrene and polydimethylglutarimide and the acid concentration being homogeneous with respect to a horizontal surface of a substrate to which the solution is applied; and a silicon-rich layer, the layer being formed above the solution by the reaction of an organosilane with the acid.

Silylated photo-resist layer and planarizing method

A Ge--Si MOS transistor for high speed, high density applications in which a thin layer of silicon (Si) is doped to have a concentration of germanium (Ge) ions which is preferably between 10 and 30%. The germanium doped silicon is formed on a layer or substrate of insulator. Optional silicidation of the drain and source regions improves conductivity therein and the use of shallow SIMOX processing technologies results in a more cost-effective and rapid fabrication process.

GE-SI SOI MOS transistor and method of fabricating same

Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the Latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.

Semiconductor with implanted dielectric layer having patched pin-holes

The method is a technique for making silicon-on-insulator (SOI) wafers which are suitable for use in the production of CMOS devices, which are designed to operate with low power and low voltage. The method of the invention provides high quality SOI material at relatively low cost by implanting, in one form of the invention, a very low dose of nitrogen or oxygen ions at a very low energy into silicon, and thereafter diffusing oxygen during an annealing process to form a continuous buried layer of silicon-oxy-nitride (Si.sub.x,O.sub.y N.sub.z, or SON) or SiO.sub.2. The process includes using an ion beam to implant ions into the substrate, thereby damaging a region of the crystal. The feed gas for the ion beam may be a variety of nitro-oxide gases, such as NO, N.sub.2 O, NO.sub.2, as well as a simple mixture of nitrogen and oxygen gases. Other elemental ions may be implanted to create the desired crystal defects. The wafer is then annealed in an atmosphere that allows the diffusion of the second species, usually oxygen, through an upper layer of the substrate to the region wherein the crystal has been damaged, wherein the second species reacts with the damaged crystal material to form a thin layer of insulating material which is located a very small distance below the surface of the wafer.

Method of treating silicon to obtain thin, buried insulating layer

The invention provides an improved planarizing methodology for forming high-definition photolithographic masks of the type used in semiconductor integrated circuit manufacturing. A layer of planarizing photoresist is first applied to the surface topography of a semiconductor wafer substrate and shallow-penetrating radiation is then used to irradiate the surface of the photoresist. The radiation creates a blanket irradiated layer, adjacent the surface of the resist, consisting of an acid and resist in solution. The acid/resist solution readily absorbs and incorporates silicon. Next, the wafer is exposed to a silicon-containing compound, or softbaked in a silicon-containing environment, creating a silicon-enriched region adjacent the surface of the photoresist. An imaging resist is then applied to the resist, and a photolithographic mask is formed in the imaging resist. An etching step transfers the mask to the silicon-enriched region of the photoresist. The remaining areas of the silicon-enriched layer are exposed to an oxygen plasma which converts the silicon-enriched areas to silicon dioxide. The method of the invention produced high-definition mask lines and avoids the defect densities associated with conventional tri-layer processing using SOG.

Method of forming a pattern of silylated planarizing photoresist

A graduated concentration profile is used for defining a buried isolation region in a semiconductor device. Smaller concentrations of dielectric-defining particles are used for implantation at the deepest levels of the isolation region in order to reduce the defect density in an overlying epi layer.

Graded implantation of oxygen and/or nitrogen constituents to define

A planarizing technique comprising: coating a topography overlying a substrate with a planarizing resist layer; softbaking the planarizing resist layer in the presence of a silicon-containing vapor or liquid; coating the planarizing resist layer with an imaging resist layer; softbaking the imaging resist; selectively exposing the imaging resist layer to light; developing the imaging resist layer; and etching the planarizing layer. The planarizing layer may comprise novolacs and other organic polymers used conventionally in lithographic processes. Specifically, the polymer is selected from the group consisting of a novolac, polymethylmethacrylate, polydimethylglutarimide and polyhydroxystyrene. The planarizing layer may further comprise any organic acid moiety that is compatible with the solvent used to dissolve the resin. In particular, the acid moiety is indole-3-carboxylic acid. In another aspect, the invention comprises a silylated planarizing resist. The resist comprises: a solution of a polymer and an acid, the polymer being selected from the group consisting of a novolac, polymethylmethacrylate, polyhydroxystyrene and polydimethylglutarimide and the acid concentration being homogeneous with respect to a horizontal surface of a substrate to which the solution is applied; and a silicon-rich layer, the layer being formed above the solution by the reaction of an organosilane with the acid.

Silylated photoresist layer and planarizing method

The invention provides a method of forming shallow SIMOX (Separation by IMplantation of OXygen) substrates by implantation of molecular oxygen ions (O.sub.2 +), instead of implanting atomic oxygen ions (O+) as is done in prior art SIMOX processes. Use of molecular oxygen ions (O.sub.2 +) doubles the yield of oxygen atoms implanted for each unit of electric charge deposited in the wafer. The resultant structure, after annealing, has a defect density which is not substantially different from SIMOX processing using atomic oxygen ions (O+). An alternative method for implanting molecular nitrogen ions is also disclosed.

Shallow SIMOX processing method using molecular ion implantation

A graduated concentration profile is used defining a buried isolation region in a semiconductor device. Smaller concentrations of dielectric-defining particles are used for implantation at the deepest levels of the isolation region in order to reduce the defect density in an overlying epi layer.

Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.

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Vancouver, WA, United States of America

Tatsuo Nakato