Nec Corporation

Nippon Electric Co., Ltd.

Tatsunori Murotani

Tadahiko Sugibayashi

Isao Naritake

Satoshi Utsugi

A data refresh is indispensable for a semiconductor dynamic random access memory device, and electric charges are recycled from bit line pairs for a row of memory cell arrays to power supply lines for bit line drivers associated with the next row of memory cell arrays and from bit line pairs for the next row of memory cell arrays to power supply lines for the row of memory cell arrays, thereby reducing power consumption in the data refresh.

Low power consumption semiconductor dynamic random access memory device

The memory cell array in accordance with the invention is divided into several memory cell array portions, each memory cell array portion having refresh period determined so as to be adapted to a memory cell having minimum data retention time among memory cells therein. The invention can greatly reduce consumption of electrical power by refresh relative to the conventional memory cell array.

Dynamic semiconductor memory with refresh function

A semiconductor memory has a first internal circuit operated by an external source, a second internal circuit operated by an internal source which outputs an internal voltage lower than that of the external source and a voltage-down-converter supplying the internal source to the second internal circuit. The voltage-down-convertor includes a reference-voltage-source circuit and voltage-down-circuit. The reference-voltage-source circuit is made up of a standard-voltage-generation-circuit generating a standard voltage equal to a standard internal source voltage, a gate circuit outputting the standard voltage as the reference voltage when a control signal from outside is of a first logic level, a dividing circuit outputting voltages which are lower or higher than the standard internal source voltage and a selection circuit which selects one of the output voltages of the dividing circuit when the control signal is of a second logic level.

Semiconductor memory

A semiconductor memory device comprises memory cell array, bit line pairs respectively coupled to the columns of the memory cells, sense amplifier circuits operative to increase small differences in voltage level on the bit line pairs, first and second voltage lines supplying a high voltage level and the ground voltage level through the sense amplifier circuits to the bit line pairs for increasing the small difference, and a driving circuit operative to activate the sense amplifier circuits, wherein the driving circuit comprises an equalizing circuit for equalizing the first and second voltage lines to an intermediate voltage level, a first transistor coupled between the first voltage line and a source of an external voltage level higher than the high voltage level, a second transistor providing a conduction path between a source of the second voltage level and the second voltage line in the presence of a control signal and isolating the second voltage line from the source of the second voltage level in the absence of the control signal, and a control circuit causing the first transistor to produce the high voltage level in the presence of another control signal and to isolate the first voltage line from the source of the external voltage level in the absence of the control signal.

Semiconductor memory device having a driving circuit provided in

A decoder circuit comprises a P type substrate in which an N well is formed, a plurality of P channel word line drive transistors each having a gate supplied with a signal having a level corresponding to an address signal and a source-drain connected between a word line and an input terminal of a signal driving the word line and the N well is biased with a biasing signal different from said word line drive signal. Gate insulating films of the word line drive transisters are not subjected to breakdown by a high voltage application thereto. Further, since there is no extra load applied to the clock signal, it is possible to make the word line drive at high speed.

Decoder circuit

For preventing sense amplifier circuits associated with memory cells from misjudgment, there is proposed a semiconductor memory device comprising protection cells formed between memory cell array and peripheral circuits, and the protection cells are coupled to an additional bit line pair precharged to a predetermined voltage level approximately equal to those of bit line pairs coupled to the memory cells, so that no difference voltage takes place between the additional bit line pair and the neighboring bit line pair, thereby eliminating a difference in characteristics of the sense amplifier circuits coupled thereto.

Semiconductor memory device with protection cells

A semiconductor memory device which has low noise structure and is operable with high stability. The memory device employs a plurality of single transistor memory cells each composed of a capacitor and a transistor coupled between one electrode of the capacitor and a bit line, the other electrode of the capacitor being supplied with a predetermined potential. The other electrode is made of a refractory metal, and a relatively low sheet resistance is provided to the other electrode of the capacitor so that the potential fluctuation at the other electrode of the capacitor is suppressed.

Semiconductor memory device with low-noise structure

A dynamic memory which can accurately precharge a pair of bit lines to a potential equal to half the power supply voltage and which has improved detection characteristics is disclosed. The dynamic memory is of the type in which a precharge potential of a pair of bit lines is generated by short-circuiting the pair of bit lines after the pair of bit lines are discriminated into the power supply voltage and the reference voltage (ground). A compensation capacitor is provided for the pair of bit lines. The compensation capacitor is charged to the power supply voltage and the charged compensation capacitor is operatively connected to the pair of bit lines when they are short-circuited to thereby raise the potential on the bit lines to half the power supply voltage.

Dynamic memory with improved arrangement for precharging bit lines

A redundant type memory circuit having a normal memory cell array, a first decoder circuit for operatively accessing normal array, a redundant memory cell array, a second decoder circuit for accessing the redundant array, and a programmable timing control circuit for enabling the first decoder circuit at a first delay period when no faulty cell exists in the normal array and at a second longer delay period when a faulty cell exists in the normal array.

Redundant type memory circuit with an improved clock generator

A logic circuit provided with a desired hysteresis characteristic in its input-output characteristics is disclosed. The circuit comprises a logic section including a first depletion type field effect transistor operating as a load element and at least one input field effect transistor of an enhancement type, a series circuit of a second depletion type field effect transistor and a switching transistor connected in series with respect to the first depletion type field effect transistor and means responsive to an output signal of the logic section for controlling the switching transistor so as to provide a hysteresis in the input-output characteristic of the circuit.

Logic circuit with improved hysteresis characteristics

A memory circuit provided with a temperature-compensated internal refresh function is disclosed. The memory circuit comprises an oscillator circuit having a frequency characteristic with a positive temperature coefficient and means for generating refresh signals on the basis of the oscillation period of the oscillator circuit, wherein refresh of the memory circuit is achieved with the refresh signals.

Temperature responsive refresh control circuit

A logic circuit comprises a first and a second inverter for producing a first and a second inverted signal, respectively, one of which varies faster with a common variable input signal than the other. Responsive to the first inverted signal, a first buffer circuit produces a first output signal having a phase opposite to the input signal. Supplied with the second inverted signal, a second buffer circuit produces a second output signal having a phase same as the input signal. Preferably, the first buffer circuit comprises a depletion field effect transistor controlled by the first inverted signal and an enhancement field effect transistor controlled by the input signal. The second buffer circuit comprises an enhancement field effect transistor controlled by the second inverted signal and a depletion field effect transistor controlled by the input signal. More preferably, each of the first and the second inverters comprises a driving and a load field effect transistor. Amplification characteristics are rendered different from each other between the driving transistors of the first and the second inverters and/or between the load transistors of the respective inverters so as to make the first inverted signal have a level higher than the second inverted signal within an interval of time during the variation of the input signal.

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Tokyo, Japan

Tatsunori Murotani