Kioxia Corporation

Toshiba Memory Corporation

Taro Shiokawa

Kiwamu Sakuma

Kazuhiro Nojima

Keiko Sakuma

Shigeki Kobayashi

Masahisa Sonoda

Tomonori Kajino

Kenichi Kadota

Megumi Shibata

A transistor includes an upper electrode; a lower electrode; a gate electrode disposed between the upper electrode and the lower electrode; and a columnar portion penetrating the gate electrode and provided between the upper electrode and the lower electrode. The columnar portion includes a tubular gate insulating film and a semiconductor layer, the tubular gate insulating film disposed at a first distance away from the upper electrode and in contact with the gate electrode. The semiconductor layer is embedded in the tubular gate insulating film and between the gate insulating film and the upper electrode and in contact with the upper electrode.

Transistor, semiconductor memory device, and manufacturing method for transistor

A semiconductor device according to the embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode opposed to the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided between the gate electrode and the first electrode; and a second insulating layer provided between the gate electrode and the second electrode and having an oxygen atom concentration lower than an oxygen atom concentration of the first insulating layer.

Semiconductor device and semiconductor memory device

According to one embodiment, there is provided a measuring apparatus including a measurement section and a control section. The measurement section is configured to acquire a response from a sample. The control section is configured to compare a loading obtained by performing principal component analysis in advance with a first evaluation-use loading obtained by performing principal component analysis onto the response acquired from the sample, and to generate a first reliability index for measurement using principal component analysis, in accordance with a comparison result.

Measuring apparatus

According to one embodiment, a semiconductor memory device includes: a plurality of first interconnect layers including first and second conductors; a second interconnect layer arranged above the first interconnect layers; a third interconnect layer arranged adjacently to the second interconnect layer; a first pillar passing through the first interconnect layers and the second interconnect layer; a second pillar passing through the first interconnect layers and the third interconnect layer; and a third pillar arranged between the second interconnect layer and the third interconnect layer and passing through the first interconnect layers. The second conductor covers a top surface and a bottom surface of the first conductor, and a side surface of an end portion of the first conductor.

Semiconductor memory device and method of manufacturing the same

A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.

Semiconductor storage device

According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.

Growing community of inventors

Nagoya, Japan

Taro Shiokawa