Globalfoundries U.S. Inc.

Globalfoundries Inc.

Tao Chu

Bingwu Liu

Ayse M Ozbek

Guowei Xu

Balaji Kannan

Katsunori Onishi

Bala S Haran

Vishal Chhabra

Haiting Wang

Hong Yu

Brian Joseph Greene

Man Gu

Wei Hong

Wenjun Li

Dali Shao

Wei Ma

Rongtao Lu

Xiaoli He

Liqiao Qin

The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

Stacked-gate transistors

One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.

Methods of forming an IC product comprising transistor devices with different threshold voltage levels

Structures for field-effect transistors and methods of forming a structure for field-effect transistors. A semiconductor layer includes first and second channel regions, a first field-effect transistor has a first gate dielectric layer over the first channel region, and a second field-effect transistor has a second gate dielectric layer over the second channel region. The first and second channel regions are each composed of an undoped section of an intrinsic semiconductor material, the first gate dielectric layer contains a first atomic concentration of a work function metal, and the second gate dielectric layer contains a second atomic concentration of the work function metal that is greater than the first atomic concentration of the work function metal in the first gate dielectric layer.

Field-effect transistors with independently-tuned threshold voltages

One illustrative IC product disclosed herein includes a semiconductor substrate and a first transistor device formed on the semiconductor substrate. The first transistor device comprises a first gate structure. The first gate structure comprises a gate insulation layer, a first layer of titanium nitride (TiN) positioned above the gate insulation layer, a layer of titanium silicon nitride (TiSiN) positioned above the first layer of TiN and a second layer of titanium nitride (TiN) positioned above the layer of TiSiN.

Low leakage gate stack for a transistor device and methods of making an IC product that includes such a transistor device

One illustrative method disclosed herein includes forming at least one fin, forming a first recessed layer of insulating material adjacent the at least one fin and forming epi semiconductor material on the at least one fin. In this example, the method also includes forming a second recessed layer of insulating material above the first recessed layer of insulating material, wherein at least a portion of the epi semiconductor material is positioned above a level of the upper surface of the second recessed layer of insulating material, and forming a source/drain contact structure above the second recessed layer of insulating material, wherein the source/drain contact structure is conductively coupled to the epi semiconductor material.

Methods of forming source/drain regions of a FinFET device and the resulting structures

Disclosed is a metal gate (e.g., a replacement metal gate (RMG) for a field effect transistor (FET) and a method of forming the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and chamfer processes to selectively adjust the heights of conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall gate height control and gate quality particularly when the metal gate has a small critical dimension (CD) and/or a high aspect ratio (AR). The method can also include using different etch techniques during the different chamfer processes and, particularly, when different materials and/or different material interfaces are exposed to an etchant in order to ensure an essentially uniform etch rate of the conformal metal layer(s) at issue in a direction that is essentially vertical.

Metal gate for a field effect transistor and method

The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

Cut inside replacement metal gate trench to mitigate N-P proximity effect

Growing community of inventors

Portland, OR, United States of America

Tao Chu