Macronix International Co., Ltd.

Other

Tao Cheng Lu

Wen Jer Tsai

Chih Chieh Yeh

Han Chao Lai

Mam Tsung Wang

Chih Yuan Lu

Yao Wen Chang

Hung-Sui Lin

Chin Hsi Lin

Meng Huang Liu

Ful Long Ni

Mam-Tsung Wang

Chun-Hsiang Lai

Yi Ying Liao

Hsing Lan Lung

Wen-Jer Tsai

Hung-Yueh Chen

Nian-Kai Zous

Chung Ju Chen

I Chen Yang

Sing Su

Chu Yung Liu

Hon Sui Lin

Hsing Wen Chang

Nian Kai Zous

Wen Her Tsai

Hung Yueh Chen

Guan Wei Wu

Chun Hsiang Lai

Der Shin Shyu

Shi Xian Chen

A semiconductor structure has a MOSFET and a substrate to accommodate the MOSFET. The MOSFET has a gate, a source, and a drain in the substrate. A first substrate region surrounding the MOSFET is doped with a stress enhancer, wherein the stress enhancer is configured to generate a tensile stress in the MOSFET's channel and the tensile stress is along the channel's widthwise direction.

Semiconductor structure

A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line to a first voltage, biasing a string select transistor to a second voltage; and ramping down the string select transistor to the first voltage. In particular, the second voltage is higher than the first voltage.

Method of programming a flash memory by enhancing the channel voltage of a program-inhibit bit line with a boosted inhibit scheme

A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Method for manufacturing a multiple-bit-per-cell memory

An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage, so as to discharge the electrostatic charges. The anti-latch-up circuit has two terminals, which are respectively coupled to the voltage source and the ground voltage, and another connection terminal, used to send an anti-latch-up signal to the SCR for changing the activating rate. The latch-up phenomenon is avoided.

Electostatic discharge protection circuit coupled on I/O pad

A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Integrated code and data flash memory

Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge, in the erased state than i.n the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.

Method and apparatus for protection from over-erasing nonvolatile memory cells

A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.

Method and apparatus for operating charge trapping nonvolatile memory

A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a single memory cell, a column or NOR-connected memory cells, and a virtual ground array of memory cells.

Method and apparatus for operating nonvolatile memory in a parallel arrangement

A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.

Method and system for self-convergent erase in charge trapping memory cells

A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.

Method for programming programmable eraseless memory

Method for manufacturing a programmable eraseless memory

Electrostatic discharge protection circuit coupled on I/O pad

One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit. The present invention also provides a method for sensing and reading at least one bit in a nonvolatile memory comprising applying a bias voltage to the memory, detecting a threshold voltage or read current, comparing the threshold voltage with a reference voltage or comparing the read current with a reference current, and identifying the at least one bit as erased or programmed.

Nonvolatile memory cell and operating method

The invention provides a nonvolatile memory and corresponding method having an optimal memory erase function and, more particularly, a method for erasing a nonvolatile memory comprising a source, a gate, a drain, a channel and a trapping layer. The method according to a preferred embodiment of the invention generally comprises the steps of applying a non-zero gate voltage to the gate, applying a non-zero source voltage to the source, applying a non-zero drain voltage to the drain in each erase shot wherein the drain voltage is generally higher in magnitude than the source voltage, generating hot holes in the nonvolatile memory, injecting the generated hot holes in the trapping layer near drain junction, and accordingly erasing the nonvolatile memory. The erase method according to a further embodiment of the invention comprises a verifying step after each erase shot for verifying the memory erase for the nonvolatile memory, and repeating the process steps according to the invention if the memory erase is not verified.

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Hsinchu, Taiwan

Tao Cheng Lu