Hitachi-High-Technologies Corporation

Tamao Ishikawa

Yutaka Tandai

Katsuhiko Ichinose

Tsunehiro Sakai

Shigeki Kurihara

Yuji Takagi

Takehiro Hirai

Yuichi Hamamura

Seiji Isogai

Tomohiro Funakoshi

Shigetoshi Sameshima

Kazuhisa Hasumi

Koichi Hayakawa

Kazunori Nemoto

A defect image processing apparatus uses a normalized cross correlation to image-match a layout image () acquired from a design data with an image acquired by removing, from a defect image (), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image () on the display device. In the displayed layout image & defect image (), not only the layout image, the layer of which is the same as that of the defect image (), but also a layout image of another layer is displayed superimposed on the defect image (). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.

Defect image processing apparatus, defect image processing method, semiconductor defect classifying apparatus, and semiconductor defect classifying method

A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.

Semiconductor defect classifying method, semiconductor defect classifying apparatus, and semiconductor defect classifying program

There is provided an evaluation object pattern determining apparatus capable of determining local patterns to be evaluated. The apparatus is for use in a pattern evaluating system storing patterns of a LSI chip as CAD data, picking out coordinates of local patterns whose process margin is small from the CAD data by way of simulation and assisting observation of the local patterns produced in a fabrication line. The apparatus includes a risk level map creating section for creating risk level maps in which risk areas are disposed. The risk area is assigned with a risk level obtained by digitizing that the risk area is an area whose process margin is smaller than other areas. The apparatus also includes a superimposition processing section for superimposing the coordinates of the local patterns with the risk level map to pick out the coordinates of the local patterns located within the risk area.

Evaluation object pattern determining apparatus, evaluation object pattern determining method, evaluation object pattern determining program and pattern evaluating system

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Hitachinaka, Japan

Tamao Ishikawa