Kabushiki Kaisha Toshiba

Takuya Kouno

Tatsuhiko Higashiki

Hiroshi Nomura

Shigeki Nojima

Takashi Sato

Takashi Sakamoto

Ichiro Mori

Yoshiyuki Shioyama

Kazuo Tawarayama

Noboru Yokoya

An aligner evaluation system includes (a) an error calculation module configured to calculate error information on mutual optical system errors among a plurality of aligners; (b) a simulation module configured to simulate device patterns to be delineated by each of the aligners based on the error information; and (c) a evaluation module configured to evaluate whether each of the aligners has appropriate performances for implementing an organization of a product development machine group based on the simulated device pattern.

Aligner evaluation system, aligner evaluation method, a computer program product, and a method for manufacturing a semiconductor device

A design system of an alignment mark for manufacturing a semiconductor device includes a memory which stores at least mark data including pattern information regarding plural kinds of marks and process data including condition information of manufacturing processes, and a first process simulator which simulates a substrate structure before patterning based on the process data, the substrate structure being formed in an identified manufacturing process. Moreover, the design system includes a second process simulator which simulates a processed shape of an identified mark after the patterning based on the simulated substrate structure and the process data, the mark formed in the manufacturing process, a signal waveform simulator which simulates a detection signal waveform of the mark, the waveform being obtained from the simulated processed shape of the mark, and a signal evaluation device which evaluates a suitability of the mark for the identified manufacturing process based on the simulated detection signal waveform.

Design system of alignment marks for semiconductor manufacture

An exposure method forms, in a shot area on a reticle, marks to measure arrangement errors that may occur between adjacent device patterns, transfers the marks from the reticle onto a wafer through exposure and development processes using an exposure system, measures arrangement errors according to the marks on the wafer, calculates four error components from the measured arrangement errors, and corrects the exposure system according to the calculated error components. This method eliminates superposition errors from the next exposure process, thereby effectively using the shot areas of exposure systems.

Exposure method, reticle, and method of manufacturing semiconductor device

A plurality of bars-in-bars marks are formed. Each mark has four small patterns and four large patterns arranged in a direction of a straight line and a direction perpendicular thereto. The straight lines of the respective bars-in-bars marks are disposed at angles of 0&deg;, 30&deg; and 60&deg;.

Aberration measuring method, aberration measuring system and aberration measuring mask

In an alignment apparatus, an alignment mark formed on a substrate is illuminated through an illuminating optical system, and an image of the alignment mark is projected onto a light receiving surface of a CCD camera through an enlarging optical system. The enlarging optical system includes a parallel flat plate, the inclination of which can be adjustable, for parallel-translating an eccentric component of coma.

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Kanagawa, Japan

Takuya Kouno