Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Takuya Futase

Yuji Takahashi

Noritaka Fukuo

Katsuo Yamada

Tomoyasu Kakegawa

Kiyokazu Shishido

Fumiaki Toyama

Shin Kikuchi

Kotaro Jinnouchi

Keita Kumamoto

Masami Uozaki

Shunsuke Watanabe

Hiroto Ohori

Christopher John Petti

Akio Nishida

Seje Takaki

Eiji Hayashi

Yoichiro Tanaka

Teruyuki Mine

Yoko Furihata

Hiroaki Koketsu

Eiichi Fujikura

Toshihiro Iizuka

Hirotada Tobita

Toshiyuki Sega

Hidetoshi Nakamoto

Hidehito Koseki

Toshihide Tobitsuka

Kan Fujiwara

Shunsuke Akimoto

Satoshi Kamata

Kazushi Komeda

Susumu Okazaki

A method is provided that includes forming a cell film stack on a substrate of a wafer, the cell film stack comprising a top silicon layer, depositing a sacrificial layer onto the top silicon layer, etching the cell film stack and the sacrificial layer to form a plurality of pillars, depositing a dielectric to fill in gaps between the plurality of pillars, planarizing the wafer to a predefined thickness for the sacrificial layer, removing the sacrificial layer, depositing nickel onto the wafer to form a nickel layer, annealing the wafer to form a di-nickel silicide layer between the nickel layer and the top silicon layer, wet etching unreacted nickel of the nickel layer to expose the di-nickel silicide layer, and annealing the wafer to form a nickel monosilicide layer from the di-nickel silicide layer and the top silicon layer, the nickel monosilicide layer forming a monosilicide electrode.

Low resistance monosilicide electrode for phase change memory and methods of making the same

A cross-point memory device includes first conductive line structures laterally extending along a first horizontal direction, an array of memory pillar structures overlying top surfaces of the first conductive line structures, such that each of the memory pillar structures includes a respective memory element, and second conductive line structures laterally extending along a second horizontal direction and overlying top surfaces of the array of memory pillar structures. At least one of the first conductive line structures and the second conductive line structures each includes a respective aluminum-containing rail and a respective metallic cap strip in contact with a top surface of the respective aluminum-containing rail.

Memory array containing capped aluminum access lines and method of making the same

This disclosure relates to a low-resistance monosilicide electrode and method of making the monosilicide electrode. A cell film stack is first formed on a substrate of a wafer. The top layer of this cell film stack is silicon. The cell film stack is then etched to form at least one pillar. Dielectric is deposited to fill the gaps between the pillars. The wafer is then planarized to expose the top silicon layer. The exposed top silicon layer is converted into a nickel monosilicide layer by way of a thermal solid-state reaction between nickel and the silicon layer. This nickel monosilicide layer forms the monosilicide electrode.

A resistive memory cell includes a barrier layer containing at least one of silicon and germanium, and a metal oxide layer including an oxide of a metal element that provides a reversible chemical reaction under a bidirectional electrical bias at an interface with the barrier material layer. The reversible chemical reaction is selected from a silicidation reaction between the barrier material layer and the metal element, a germanidation reaction between the barrier material layer and the metal element, oxidation of the metal element, and reduction of the metal element.

Resistive memory cell programmed by metal alloy formation and method of operating thereof

An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.

Three-dimensional resistive random access memory containing self-aligned memory elements

A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.

Buried etch stop layer for damascene bit line formation

Isolation is provided by forming a first trench, depositing a cover layer on the bottom and sidewalls of the first trench, selectively removing the cover layer from the bottom and forming a second trench extending from the bottom of the first trench. The second trench is then substantially filled by thermal oxide formed by oxidation and the first trench is subsequently filled with a deposited dielectric.

Double trench isolation

An initial etch forms a trench over first contact areas of a plurality of NAND strings, the initial etch also forming individual openings over second contact areas of the plurality of NAND strings. Material is added in the trench to reduce an area of exposed bottom surface of the trench while maintaining the individual openings without substantial reduction of bottom surface area. Subsequent further etching extends the trench and the plurality of individual openings.

Source line formation and structure

A wide trench having a width Wand narrow trenches having a width Wthat is less than Ware formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.

Metal line with increased inter-metal breakdown voltage

Dummy bit lines of are formed in a sacrificial layer at locations where bit lines are to be formed, with bit lines separated by trenches that extend through the sacrificial layer. Enclosed air gap structures are formed in the trenches between the dummy bit lines. Subsequently, the dummy bit lines are replaced with metal to form bit lines.

Early bit line air gap formation

Wide and narrow mandrels that are used to form sidewall spacers for patterning are formed in a sacrificial layer with openings in wide mandrels near sides of the wide mandrels. Sidewall spacers are formed on the sides of mandrels and the sacrificial layer is removed. The sidewall spacers are then used for patterning of underlying layers.

Conductive line structure with openings

Contact holes are constrained to their designated active areas by etch-resistant walls so that they cannot contact adjacent active areas. Etch-resistant walls provide outer limits for any contact hole bending that may occur and thus keep contact holes substantially vertical. Mask openings for contact hole formation may be large so that they overlap etch-resistant walls.

Contact hole collimation using etch-resistant walls

A three-dimensional (3D) non-volatile memory array having a silicide bit line and method of fabricating is disclosed. The fabrication technique may comprise forming a metal silicide for at least a portion of the bit line. The device has reversible resistivity material between the word lines and the bit lines. The reversible resistivity material may be a metal oxide. The metal that is used to form the silicide may serve as an oxygen scavenger to draw oxygen away from the silicon, thus preventing formation of silicon oxide between the reversible resistivity material and the bit line. The metal silicide may also help prevent formation of a depletion layer in silicon in the bit line.

Silicided bit line for reversible-resistivity memory

A pattern of parallel lines defines first regions where no conductive material is to be located, a distance between adjacent lines in the first regions being smaller than a predetermined distance, and defines second regions where conductive material is to be located, a distance between adjacent lines in the second regions being larger than the predetermined distance. A subsequent layer caps air gaps between lines in the first regions. Conductive material is then deposited and planarized to form lines of conductive material in the second regions.

Air gaps structures for damascene metal patterning

A first depression and a second depression are formed in an upper surface of a first metal layer. A dielectric layer is formed over the first metal layer. Subsequently, a wide trench is formed in the dielectric layer, the wide trench extending deeper in a first outer region and in a second outer region than in a central region located between the first outer region and the second outer region, the first outer region overlying the first depression and the second outer region overlying the second depression.

Growing community of inventors

Yokkaichi, Japan

Takuya Futase