Kabushiki Kaisha Toshiba

Takuya Fujimoto

Yoshiharu Hirata

Akira Umezawa

Hideki Takeuchi

Kazuhisa Sakihama

Yoshiaki Hashiba

Takehiro Hasegawa

Akihiro Sueda

Masaki Ichikawa

Shigeru Yamada

Nozomi Kasai

A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.

Semiconductor integrated circuit device

A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects commonly the control gates of the first MOS transistors in a same row. The first charge pump circuit is activated and generates a first voltage in a write operation and erase operation. The first voltage is supplied with either the well region or the word lines. The discharge circuit, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage.

Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same

A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same

A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. The first MOS transistors are connected commonly to the write bit lines and read bit lines. The latch circuits are provided for the write bit lines and hold write data for the memory cells. The n-channel MOS transistor transfer '1' data to the latch circuits in a data latch operation. The voltage setting circuits supply a potential corresponding to '0' data to the write bit lines in a read operation. In a data latch operation, the latch circuit corresponding to the write bit line connected to the memory cell into which &#x201c;0&#x201d; data is to be written latches the potential supplied to the write bit lines in a read operation.

Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, a control method thereof, and a memory card including the same

A semiconductor memory device includes a memory cell array, word lines, bit lines, a control circuit, and a measurement circuit. The memory cell array has memory cells including a floating gate. The control circuit performs first control to collectively shift the threshold voltages of the memory cells to within a predetermined range with a first level as an upper limit, second control to shift a lower limit of the threshold voltages toward a second level lower than the first level, and third control to shift the lower limit to a third level. The measurement circuit measures the elapsed time from the start of the second control. The control circuit repeats the second control, and then terminates the second control when the lower limit reaches the second level or the elapsed time measured by the measurement circuit reaches the predetermined time and performing the third control.

Semiconductor memory device having memory cells with floating gates and memory cell threshold voltage control method

A semiconductor memory device including: a first memory cell array including a plurality of memory cells, a first switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the first memory cell array, a latch circuit for latching the data transferred from the first switch circuit, a first write selector circuit for transferring the data transferred from the latch circuit, a first bit line connected to at least one of the plurality of memory cells and receiving the data transferred from the first write selector circuit, a second memory cell array including a plurality of memory cells that are different from the plurality of memory cells arranged in the first memory cell array, a second switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the second memory cell array, a second write selector circuit connected to the second switch circuit and transferring the data transferred from the second switch circuit, and a second bit line connected to at least one of the plurality of memory cells arranged in the second memory cell array.

Semiconductor memory device having first and second memory cell arrays and a program method thereof

A voltage stepup circuit having a plurality of setup circuit units connected in stages between an input voltage node and a stepup voltage node. Each circuit unit comprises at least two first and second MOS transistor T1 and T2. Each of first stepup capacitors is connected between a first clock signal supply node and a first connection node at which the drain and gate of a corresponding one of odd-numbered MOS transistors, of a plurality of MOS transistors connected in series through the plurality of stepup circuit units, are connected together. Each of second stepup capacitors is connected between a second connection node at which the drain and gate of a corresponding one of even-numbered MOS transistors of the plurality of MOS transistors connected together and a second clock signal supply node for supplying said second connection node with a second clock signal whose pulse width does not overlap in time with that of the first clock signal. A first clock amplitude control circuit limits the amplitude of the first clock signal to be supplied to the first clock signal supply node to a predetermined level and applies the first amplitude-limited clock signal to the first clock signal supply node. A second clock amplitude control circuit limits the amplitude of the second clock signal to be supplied to the second clock signal supply node to a predetermined level and applies the second amplitude-limited clock signal to the second clock signal supply node.

Voltage stepup circuit for integrated semiconductor circuits

A semiconductor memory device in which a data line and a holding circuit for storing data thereon are connected through a transmission gate comprised of an N-type MOS transistor and a P-type MOS transistor, wherein the semiconductor memory device comprises an initial potential setting circuit for setting an initial potiential on the data line prior to readout operation of data from the holding circuit; and a control circuit operative to allow the both transistors of the transmission gate to be turned on at the time of writing data into the holding circuit, and to allow one of the transistors to be turned on at the time of reading data from the holding circuit. Where a hold potential changes when data in the holding circuit has been read out onto the data line, such a change in the hold potential increases on resistance of one of the transistors which has been turned on of the transmission gate. As a result, this change in the hold potential in held down to a small value, so it does not reach the threshold voltage of the holding circuit.

Semiconductor memory device

An oscillator including a CMOS inverter, a feedback reactance connected between the input and output terminals of the CMOS inverter and a CMOS transfer gate connected as a feedback resistor between the input and output terminals of the CMOS inverter, a power source terminal section to which an external voltage is applied, and a power control unit for converting the external voltage to a first internal voltage which is supplied as a power source voltage to the CMOS inverter. The power control unit converts the external voltage to a second internal voltage independently from the first internal voltage and supplies the second internal voltage as a gate control voltage to the CMOS transfer gate.

Oscillation circuit

A first node is connected to an external power source via a switch. A second node is connected to an internal power source whose voltage is lower than that of the external power source. The first and second nodes are connected to an output node via first and second MOSFET switches. The output node is connected to a semiconductor circuit. The potentials at the first and second nodes are compared with each other by a voltage comparator connected between the output node and ground. A MOSFET is quickly turned on and off in response to the potential at the first node.

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Yokohama, Japan

Takuya Fujimoto