Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Takio Ohno

Masatoshi Kimura

Toshiaki Tsutsumi

Shuji Kodama

Takeshi Kamino

Keiichi Higashitani

Naofumi Murata

Masatoshi Taya

Hisashi Matsumoto

There is provided a semiconductor device with a configuration in which a dummy silicide areais provided in the vicinity of a non-silicide areato easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.

Capture of residual refractory metal within semiconductor device

Trenches for defining chip areas are formed on the surface of a semiconductor substrate so that outlines of side walls of each of the trenches have recesses or protrusions. Then, a sputtering film is so formed as to be continuous in an area bridging the surface of each of the chip areas and the inside surface of each of the trenches, and the semiconductor substrate is diced along lines outside the trenches.

Semiconductor device having improved trench structure

A semiconductor device having a multi-level interconnection structure is disclosed which includes a metal interconnect wire (2) formed on a surface of an interlayer dielectric film (7) serving as a base; a high-stress TEOS oxide film (5), an SOG film (3), and a low-stress TEOS oxide film (6) which are deposited as interlayer dielectric films; and a contact hole (4), thereby decreasing stresses applied from the interlayer dielectric films to the metal interconnect wire to prevent metal hillocks in the contact hole.

Semiconductor device and method of fabricating the same

A titanium silicide (4) covers surfaces of P.sup.+ -type diffusion region (7) and N.sup.+ -type diffusion region (8) to electrically connect the diffusion regions (7, 8) through the titanium silicide (4), and a surface of the titanium silicide (4) is covered with an insulation film (10). A power supply potential applied to a metal wire (2) is thereby applied to an N.sup.+ -type diffusion region (6), an N well (12) and the N.sup.+ -type diffusion region (8) through a contact hole (3) and further supplied for the P.sup.+ -type diffusion region (7) serving as a source region of PMOS transistor through the titanium silicide (4). That eliminates the need for providing any contact for supplying the diffusion regions 7 and 8 with the power supply potential to attain reduction in layout size, while preventing a latch-up. Thus, the N well-source structure of a semiconductor integrated circuit device including an SRAM with Full CMOS structure eliminates the need for providing a contact on the surfaces of the P.sup.+ -type diffusion region and the N.sup.+ -type diffusion region, to attain reduction in layout size.

Semiconductor integrated circuit device having static memory cell with

A method of manufacturing a field effect transistor can prevent increase of a sheet resistance of a metal silicide layer formed on a gate electrode. In this method of manufacturing the field effect transistor, gate electrode protective layers are formed on the gate electrodes. Using the gate electrode layers as a mask, impurity is ion-implanted into a semiconductor substrate to form source/drain regions. Thereby, the ion implantation for forming the source/drain regions can be performed without ion-implanting the impurity into top surfaces of the gate electrodes. As a result, increase of a sheet resistance of the metal silicide layer, which is formed on the top surfaces of the gate electrodes, is prevented. The use of rotary implantation and of gate protective layer including a silicon oxide film and an etching stopper layer formed on the oxide film is also disclosed.

Method of maufacturing field effect transistor

A p-type silicon substrate is provided at its main surface with n-type impurity regions with a space between each other. A gate electrode is formed on a region between the n-type impurity regions with a gate insulating film therebetween. A titanium silicide layer is formed in a region extending from a surface layer of the gate electrode to a surface layer of the n-type impurity region. The titanium silicide layer forms a local interconnection. A side wall insulating film remains on a side wall of the gate electrode on which the titanium silicide layer is not formed. Thereby, the semiconductor device can have a local interconnection which has high reliability and can be formed easily.

Growing community of inventors

Tokyo, Japan

Takio Ohno