Kabushiki Kaisha Toshiba

Takeshi Sugahara

Yasuhito Itaka

Yukihiro Fujimoto

Koichi Kinoshita

An electrostatic discharge protection circuit device includes a discharge circuit, a trigger circuit and a trigger control circuit. The discharge circuit is connected to a predetermined circuit node of a semiconductor device, and makes discharge when surge voltage is applied to the circuit node. The trigger circuit triggers the discharge circuit to start a discharge operation by the discharge circuit. The trigger control circuit controls a trigger voltage at which the trigger circuit starts a discharge operation by the discharge circuit.

Electrostatic discharge protection circuit device

Standard cells without a well potential fixing active region (T-toT-T-toT-T-toT-T-toT-) are read from a library and a circuit is temporarily designed by automatic layout wiring. Then, a change in the substrate potential is estimated from at least one of the number of transistors to be switched at the same timing in the temporarily designed circuit, the sizes of transistors, the transition probability, and the appearance probability. It is determined whether the estimated change in the substrate potential is within a reference value. If the estimated change in the substrate potential has exceeded the reference value, standard cells with a well potential fixing active region (T-T-T-andT-) are read from the library and placed in a region where the estimated change in the substrate potential exceeds the reference value. Thereafter, automatic layout wiring is done again, thereby forming a circuit.

Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential

In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.

Semiconductor integrated circuit device using four-terminal transistors

A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.

A semiconductor memory device includes first and second bit lines, memory cells each including first and second storage nodes, which are connected through selecting transistors to the first and second bit lines, respectively, a pre-charge circuit configured to pre-charge the first and second bit lines to a predetermined potential so as to read data, a hold circuit configured to maintain a potential level of the first and second bit lines, a read circuit connected to the first bit line, and a leak circuit having one terminal connected to the second bit line and another terminal connected to a ground. The leak circuit allows a current to leak from the second bit line.

Semiconductor memory device

There is disclosed a semiconductor memory device which comprises a plurality of bit line pairs each having first and second bit lines arranged in a first direction, a cell array having a plurality of SRAM cells each of which is connected between the first and second bit lines of a corresponding bit line pair via first and second storage nodes, respectively, a plurality of word lines arranged in a second direction crossing the first direction, and a data write circuit which, in the write mode, writes data into an SRAM cell selected by a word line via the first and second bit lines and, in the read mode, rewrites data read onto the first bit line from an SRAM cell selected by a word line onto the first bit line.

A content addressable memory which detects whether p (where p is an integer of 2 or more) bit sequences coincide respectively with reference bit sequences, said content addressable memory comprising: q comparison units which compares bit groups obtained by dividing the p bit sequences into q (where q is an integer of 2 or more) parts with corresponding bit groups in the reference bit sequences in p times; a precharge unit which precharges output lines of said q comparison units; and a comparison control unit responsive to a decision of noncoincidence in at least one of said q comparison units while said q comparison units are conducting an r(where r is an integer variable that is 1 or more and that is at most p&#x2212;1, and p is an integer of 2 or more) comparison operation, which stops precharging to be performed by said precharge unit at time of an (r+1)comparison operation and subsequent comparison operations.

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Fujisawa, Japan

Takeshi Sugahara