International Business Machines Corporation

Advanced Micro Devices Corporation

Sony Corporation

Sony Electronics Inc

Adeia Semiconductor Bonding Technologies Inc.

Other

Globalfoundries Inc.

Toshiba America Electronic Components, Inc.

Amd Inc.

Tessera LLC

Kabushiki Kaisha Toshiba

Advanced Micro Device, Inc.

Adeia Semiconductor Solutions LLC

Takeshi Nogami

Daniel C Edelstein

Son Van Nguyen

Chih-Chao Yang

Deepika Priyadarshini

Shom Ponoth

David V Horak

Hosadurga K Shobha

Shekhar Pramanick

Elbert Emin Huang

Benjamin David Briggs

Christopher J Penny

Shuzo Sato

Naoki Komai

Minh Van Ngo

Sergey D Lopatin

Dirk Dewar Brown

Lawrence Alfred Clevenger

Michael Rizzolo

Alfred Grill

Griselda Bonilla

Yuji Segawa

Cyril Cabral, Jr

Donald Francis Canaperi

Guarionex Morales

Balasubramanian Pranatharthiharan

Satyanarayana Venkata Nitta

Raghuveer Reddy Patlolla

Akira Yoshio

Valery M Dubin

Nicholas Anthony Lanzillo

Shyng-Tsong Chen

Ruilong Xie

Roy Rongqing Yu

Terry Allen Spooner

Wei Lin

Mitsuru Taguchi

Juntao Li

David Lee Rath

Cornelius Brown Peethala

John A Iacoponi

James John Kelly

Hiizu Ootorii

Chao-Kun Hu

Susan H Chen

Kazumichi Tsumura

Kangguo Cheng

Jeffrey P Gambino

Brent A Anderson

Theodorus E Standaert

Julien Frougier

Kenneth Parker Rodbell

Robin W Cheung

Vamsi Krishna Paruchuri

Daniel Sanders

Stephen Mark Rossnagel

Hiroshi Horikoshi

John Christopher Arnold

Simon S Chan

Takashi Kinoshita

Takamasa Usui

Albert M Young

Qiang Huang

Darryl D Restaino

Koichi Ikeda

Christopher Carr Parks

Axel Preusse

Thomas J Haigh, Jr

Balasubramanian S Pranatharthi Haran

Nobuyuki Kawakami

Masanaga Fukasawa

Jia Lee

Steven J Holmes

Vijay Narayanan

Mukta G Farooq

Paul Raymond Besser

Ping-Chuan Wang

Christian Lavoie

Andrew Herbert Simon

Imran Hashim

Kisik Choi

Thomas M Shaw

Lu You

Subhash Gupta

Ashim Dutta

Christy Mei-Chu Woo

Yun-Yu Wang

Todd P Lukanc

Huai Huang

Kai Yang

Kazuhiro Hoshino

Dominik Metzler

Geraud Jean-Michel Dubois

Patrick William Dehaven

Keishi Inoue

Philip L Flaitz

Ching-Tzu Chen

Hari Prasad Amanapu

Hiizu Ohtorii

Prasad Bhosale

An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

Self-forming barrier for use in air gap formation

Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mlevel including an Mmetal in an Mdielectric, an Mlevel above the Mlevel including an Mmetal in an Mdielectric, an embedded diffusion barrier adjacent to the Mdielectric; and a seed alloy region adjacent to the Mmetal separating the Mmetal from the Mmetal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.

Self-forming embedded diffusion barriers

A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

Backside electrical contacts to buried power rails

A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.

Substrate thinning for a backside power distribution network

Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.

Semiconductor interconnect structure with double conductors

A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.

Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer

A semiconductor structure including a first dielectric layer comprising a first conductive metal feature embedded in the first dielectric layer; and a second dielectric layer including a second conductive metal feature embedded in the second dielectric layer, the second conductive metal feature is above and directly contacts the first conductive metal feature, and an interface between the second conductive metal feature and the second dielectric layer includes a repeating scallop shape along its entire length.

Semiconductor structure having alternating selective metal and dielectric layers

A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Backside power rail integration

A semiconductor fabrication method that uses a graphene etch stop is disclosed. The method comprises forming a first set of trenches and a second set of trenches in a substrate. The first set of trenches are narrower than the second set of trenches. The method further comprises forming a graphene layer in the first and second sets of trenches. The method further comprises depositing a first conductor in the first and second sets of trenches. The method further comprises removing the first conductor from the second set of trenches using an etching process. The graphene layer acts as an etch stop for the etching process. The method further comprises depositing a second conductor in the second set of trenches. The second conductor is different than the first conductor.

Composite interconnect formation using graphene

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Method of forming copper interconnect structure with manganese barrier layer

Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

Topological semi-metal interconnects

A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Hybrid dielectric scheme for varying liner thickness and manganese concentration

An integrated circuit (IC) structure includes a dielectric layer extending along a first axis to define a length and a second axis orthogonal to the first axis to define a width. A dual-metal via is embedded in the dielectric layer. The dual-metal via includes via sidewalls surrounding a via core. An electrically conductive line extends along the first axis and on an upper surface of the dual-metal via. A side portion of the via core is co-planar with a sidewall of the electrically conductive line.

Interconnects including dual-metal vias

Copper interconnect structure with manganese barrier layer

Growing community of inventors

Schenectady, NY, United States of America

Takeshi Nogami