Kabushiki Kaisha Toshiba

Takeshi Koshiba

Tetsuro Nakasugi

Takumi Ota

Noriaki Sasaki

Ikuo Yoneda

Seiro Miyoshi

Hidefumi Mukai

Ryoichi Inanami

Nobuhiro Komine

Tatsuhiko Higashiki

Hiroyuki Mizuno

Shunko Magoshi

Kazuo Tawarayama

Kazunori Iida

In one embodiment, a method of forming a resist pattern on a substrate is provided. Information of a template pattern formed on a template based on template pattern data is obtained. A resist coating distribution is set based on the information of the template pattern. A resist is formed on a substrate based on the resist coating distribution. The template is brought into contact with the resist formed on the substrate so that the resist is filled into the template pattern formed on the template. The filled resist is cured. The template is separated from the cured resist so that a resist pattern is formed on the substrate.

Method of forming pattern, system for calculating resist coating distribution and program for calculating the same

A pattern forming method includes determining an amount of curable resin to be formed on a substrate, the curable resin having volatility, the amount of the curable resin being determined by a calculation considering volatile loss of the curable resin, the calculation being performed for each of a plurality of regions of the substrate, forming the curable resin having the determined amount on the substrate, the forming the curable resin being performed for each of the plurality of regions of the substrate, contacting the curable resin formed on the substrate with a template, the template including a pattern to be filled with the curable resin by the contacting, and curing the curable resin under a condition where the curable resin is in contact with the template.

Pattern forming method

An imprint apparatus according to embodiments includes a stage, a dropping unit that drops resist, an imprinting unit that presses a circuit pattern of a template against the resist on a transfer target substrate, an underlying position detecting unit, a correcting unit, and a dropping position control unit. The underlying position detecting unit detects a position of an underlying pattern on the transfer target substrate. The correcting unit corrects a dropping position of the resist on a basis of a position of the underlying pattern. The dropping position control unit causes the resist to be dropped onto a dropping position after correction on the transfer target substrate on the basis of corrected dropping position.

Imprint apparatus, imprint method, and manufacturing method of semiconductor device

According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.

Acceptance determining method of blank for EUV mask and manufacturing method of EUV mask

In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.

Pattern forming method, manufacturing method of semiconductor device, and template manufacturing method

According to an aspect of the invention, there is provided an electron beam drawing apparatus comprising at least one stage of a deflection amplifier and a deflection unit, a first storage section which stores shot information at a drawing time, a second storage section which stores a correction table indicating a relation between the shot information and an output voltage of the deflection amplifier, and an adjusting section which adjusts an output of the deflection amplifier based on the correction table stored in the second storage section and the shot information stored in the first storage section.

Electron beam drawing apparatus, deflection amplifier, deflection control device, electron beam drawing method, method of manufacturing semiconductor device, and electron beam drawing program

A character pattern extracting method includes ranking character patterns whose number is larger than a maximum number of character patterns in an aperture, depending on the number of reference times in design data of a semiconductor device, extracting first extraction patterns whose number is smaller than the maximum number from the large number of read character patterns in a descending order of the reference time number, defining character patterns except the first extraction patterns out of the larger number of character patterns as candidate patterns, selecting from the candidate patterns a plurality of candidate patterns whose number corresponds to a difference between the number of extracted patterns from the maximum number, and creating combinations of the selected candidate patterns, and extracting second extraction patterns included in a combination among the combinations of candidate patterns, in which a manufacturing time of the semiconductor device is most shortened.

Character pattern extracting method, charged particle beam drawing method, and character pattern extracting program

According to an aspect of the invention, there is provided an electron beam lithography apparatus including a first setting unit configured to set a drawing position on a semiconductor substrate based on layout information of the semiconductor substrate, a second setting unit configured to set a valid range on the semiconductor substrate based on shape information of the semiconductor substrate, a determination unit configured to determine whether or not the drawing position falls within the valid range, and an irradiation unit configured to irradiate the semiconductor substrate with an electron beam when the determination unit determines that the drawing position falls within the valid range.

Electron beam lithography apparatus, lithography method, lithography program, and manufacturing method of a semiconductor device

A charged particle beam exposure method is disclosed, which includes preparing an aperture mask having character apertures, correcting dimensions of designed patterns in design data in consideration of at least one of factors such as a forward scattering distance of a charged particle, a rearward scattering distance of the charged particle, a blurring of a beam of the charged particle, a dimension conversion difference of the designed patterns due to a denseness/coarseness difference of the designed patterns caused when the underlayer is processed while using the resist as a mask, and the like, allocating at least a part of a specified character aperture of the plurality of character apertures of the aperture mask to the corrected designed patterns to produce writing data, and exposing the resist to the beams of the charged particle passed through the at least a part of the specified character aperture based on the writing data.

Charged particle beam exposure method of character projection system, charged particle beam exposure device of character projection system, program for use in charged particle beam exposure device, and manufacturing method of semiconductor device

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Yokohama, Japan

Takeshi Koshiba