Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Daiichi Seiyaku Co., Ltd.

Nihon Tokusan Kabushiki Kaisha

Takeshi Hashizume

Kazuhiro Sakashita

Tatsunori Komoike

Kazutami Arimoto

Hiroki Shimano

Takeshi Fujino

Yoshisato Yokoyama

Shunya Nagata

Terukazu Yusa

Isao Takimoto

Yoshikazu Saito

Toshiaki Sano

Hirofumi Shinohara

Hiroshi Onoda

Ichiro Tomioka

Naoya Fujita

Mamoru Sakugawa

Yoshiki Tsujihashi

Takenobu Iwao

Kouji Satou

Yasufumi Mori

Yoshio Kasai

Munefumi Kanao

Sumiro Isoda

Katsumi Shinbo

Kiyoshi Irie

Kumiko Tsujihashi

Takashi Ohya

Kazuhiro Sukashita

Yoshiki Tsujzhushi

Kouji Hirano

Hideki Yahiro

Yoshifumi Ichikawa

A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.

Semiconductor device for detecting failure in address decoder

A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.

Semiconductor device and memory module

A semiconductor device includes a memory unit having a memory cell driven by a voltage applied from power supply lines VSS and VDD, and a memory unit potential controller for adjusting the potential of the voltage applied to the memory cell. The memory unit potential controller includes a first potential adjustment part provided between the power supply lines VSS and ARVSS, and a second potential adjustment part provided between the power supply lines VDD and ARVSS. Further, the memory unit potential controller adjusts the potential of the power supply line ARVSS based on a first current supplied between the power supply line VSS and a first end portion of the memory cell through the first potential adjustment part, and adjusts a second current supplied between the power supply lines VDD and ARVSS through the second potential adjustment part, in order to rapidly stabilize the potential applied to the memory cell.

Semiconductor device

Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

Memory macro and semiconductor integrated circuit device

A connection verification apparatus verifies interconnection between a plurality of logic blocks constituting a semiconductor integrated circuit or the like. It includes a connection verification section for verifying interconnection between a first logic block and a second logic block by comparing a signal level of an output terminal of the first logic block with a signal level of an input terminal of the second logic block connected to the output terminal of the first logic block. The connection verification apparatus can verify the interconnection between the two logic blocks without verifying the logic processing to the two logic blocks.

Connection verification apparatus for verifying interconnection between multiple logic blocks

In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

Refresh-free dynamic semiconductor memory device

A semiconductor integrated circuit includes a memory for holding data of a logic circuit inputs or outputs. The memory is composed of logic cells, and is placed in a logic region. Thus, the semiconductor integrated circuit can prevent forming wasted space, in which no circuit component is built, and reduce its area and power consumption. It can reduce the design period of the memory as compared with the case where hard macro cells are used.

Semiconductor integrated circuit and circuit design apparatus

A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the regular RAM can be replaced, and a control block for selecting either at least the regular RAM or the redundant RAM according to an address applied thereto, and for reading data from a memory cell of the selected RAM specified by the address. A plurality of regular RAMs can be disposed and the redundant RAM includes redundant memory elements by which defective memory elements of an arbitrary one of the plurality of regular RAMs can be replaced. The control block selects either one of the plurality of regular RAMs or the redundant RAM according to an address applied thereto, and reads data from a memory cell of the selected RAM specified by the address.

Semiconductor memory

An IP generating system includes an IP (Intellectual Property) providing apparatus and at least one development apparatus. The IP providing apparatus searches for a development apparatus installing a memory compiler to be revised with reference to applied condition data managed by a master database, and transmits the revision information as to the memory compiler to the development apparatus. The system can revise the memory compiler without requiring a user to make a decision as to the necessity of the revision of the memory compiler.

IP (Intellectual Property) generating system

In a semiconductor integrated circuit device supporting a boundary scan test, the state of an I/O cell is set under the control of a DC test control circuit through a boundary scan register utilized for the boundary scan test for setting an external terminal connected with a pad in a desired state. A semiconductor integrated circuit device allowing execution of a DC test without increasing the circuit area and signal propagation delay is provided.

Semiconductor integrated circuit devices with test circuit

DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRESH INTERVAL

A semiconductor integrated circuit device comprises a memory cell unit, and a data latch unit for temporarily latching write data, which is written into the memory cell unit by way of a normal port. A comparator reads the data, which has been written into the memory cell unit by way of the normal port, from the memory cell unit by way of a test port, and then compares the read data with the original write data latched by the data latch unit. When the comparator detects a mismatch between them, a redundant unit latches the write data to take the place of the memory cell unit and an address holding unit latches information on an address identifying a location of the memory cell unit into which the write data has been written.

Semiconductor integrated circuit device capable of repairing defective parts in a large-scale memory

In a synchronous serial transfer apparatus, the number of lines which are necessary for a serial transfer is reduced, and even when a master/slave operation is to be performed, a serial transfer is possible between any communication apparatuses without using communication apparatuses which have different structures from each other such as a master and slave apparatuses and without using a master apparatus. Communication apparatuses (TR1 to TR3) are connected parallel to each other by one communication line (TRL). A potential fixing apparatus (VC), which fixes a potential on the communication line (TRL) to 'High' or 'Low' when outputs from all communication apparatuses (TR1 to TR3) are in a 'High-Z' state, is connected to the communication line (TRL).

Synchronous serial transfer apparatus and synchronous serial transfer

An integrated circuit device is structured by a plurality of functional modules (2a, 2b) each performing a predetermined function, each functional module including a test circuit (3) for testing the corresponding module. Each test circuit comprises a scan path (3a-3d) for receiving test data from a single common input line to perform a test and outputting a test output, a tri-state buffer (4a) for controlling an output of the test output from the scan path to a single common output line, and a scan path selecting circuit (5a) for selectively driving the tri-state buffer. All the selecting circuits in the integrated circuit device are connected in series to constitute as a whole a shift register. A selecting signal of the serial data is inputted to the shift register, so that the test output of each scan path is selectively supplied to the common output line.

Integrated circuit device comprising a plurality of functional modules

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Tokyo, Japan

Takeshi Hashizume