Mitsubishi Denki Kabushiki Kaisha

Takeo Nakabayashi

Harufusa Kondoh

Hirohisa Machida

Masao Nakaya

Hideki Ando

Harufusa Kondou

Kouji Gotou

Hideki Andou

Hiroshi Segawa

Yoshitsugu Inoue

Kazuya Ishihara

Chikako Ikenaga

Harufusa Kondo

Hiroshi Kuranaga

Atsushi Kurimoto

A switch of high-speed performance can be realized not by software processing but by hardware. A control unit (,) of an NIU (,) extracts destination information (,) from a received data, and associates the destination information (,) with transfer information (,) in accordance with a table (,) to determine a line to which data is transferred. Then, the data is transferred via a bus (,) to a buffer region (,) to be temporarily stored. After transferring the data, the control unit (,) writes the information that the data to be transmitted is stored in the buffer region (,) into a cue (,), along with a pointer to an address of the data in the buffer region (,). An NIU (,) appropriately checks the cues (,) through (,). When there is data to be transmitted, the NIU (,) reads out the data from the buffer region (,) on the basis of the pointer in appropriate timing, and transmits it to a line (,).

Switch and switching method

In order to implement RT and UPC, an information pair of prev and status is stored in a memory (2) every connection. For example, prev (20.sub.i) and status (21.sub.i) are stored in a connection performing frame reassembly in an i-th region (30.sub.i). A first operation is adapted to store prev and status every time a cell is received. A second operation is adapted to read prev and status every time a timer (11) is up. A third operation is adapted to compare an elapsed time after receiving of the cell with an RT value.

ATM protocol processing method and ATM protocol processing apparatus

An interface board (2a) includes an instruction processing device (11), a board bus (4) and devices (6, 7, 8). The instruction processing device selects instructions provided on an extension bus (3) and provides them to each of the devices. This selection is made on the basis of addresses corresponding to the respective devices, which belong to an address space assigned to the entirety of the interface board (2a). Use of the board bus (4) keeps the extension bus (3) away from effects of data transfer within the interface board (2a), which requires no local CPU and which does not degrade performance of the entire system.

Interface board and instruction processing device without a local CPU

A plurality of ATM layer receiving blocks to which different applications are allocated are provided for a physical layer receiving part receiving data from an ATM transmission line and carrying out prescribed physical layer processing. The plurality of ATM layer receiving blocks incorporate data from the physical layer receiving allocated thereto are supplied to execute prescribed ATM block only when data utilized by the applications layer processing, for transmitting the processed data to corresponding higher layer processing functional blocks. A plurality of ATM layer transmission blocks responsible for different applications are provided in parallel with each other and coupled to a common ATM layer transmission block for data communication between a terminal and a network data transmission line. Thus implemented is a generic interface between an ATM layer and a physical layer in a terminal-to-network interface unit in a network in which data communication is carried out in an asynchronous transfer mode.

Protocol processor in communication network transferring data in

An application system using a large scale semiconductor integrated circuit is provided with a connection. A programmable semiconductor integrated circuit is connected to the application system via the connection and an input/output terminal of the programmable semiconductor integrated circuit. The programmable semiconductor integrated circuit is provided with a microprocessor connector, to which a probe of an ICE is connected. The programmable semiconductor integrated circuit functions as a peripheral circuit contained in the large scale semiconductor integrated circuit, so that the conventional ICE can be used.

Semiconductor integrated circuit for developing a system using a

An I/O device includes a memory and a transmission reception control circuit addresses on the memory space are assigned to the memory. The transmission reception control circuit includes a plurality of registers to which addresses on the I/O space are assigned. The memory stores data to be transmitted to an external equipment or data received from the external equipment. The plurality of registers hold control data. The memory and the transmission reception control circuit are selectively activated in response to an identification signal. The transmission reception control circuit reads out data to be transmitted to the external equipment from the memory or writes data received from the external equipment into the memory in response to the control data held in the plurality of registers.

I/O device interface having buffer mapped in processor memory addressing

A semiconductor integrated circuit serves as an interface between a CPU and the outside enabling communication between systems. More specifically, when a selector is switched to the CPU side, RAMs are accessed at random by the CPU to write data therein, and when the selector is switched to transmission controlling portion, the RAMs are serially accessed by the transmission controlling portion to read data therefrom to be transmitted. When selectors are switched to a reception controlling portion side, RAMs are serially accessed by the reception controlling portion to write data therein, and when the selectors are switched to the CPU side, the RAMs are accessed at random by the CPU to read data therefrom.

Semiconductor integrated circuit for central processor interfacing which

A semiconductor integrated circuit comprises a timing signal generating circuit for generating a plurality of timing signals in response to an externally applied reference signal, a plurality of sequential circuits to be operated in synchronism with the plurality of timing signals respectively, a plurality of combination circuits provided between the plurality of sequential circuits. Each timing signal to be applied to each sequential circuit is delayed by the time period longer than the difference between the delay amount in a combination circuit at the preceding stage and the period of a reference signal with respect to a timing signal to be applied to a sequential circuit at the preceding stage.

Semiconductor integrated circuit operating in synchronism with a

A data length detection device for detecting the byte length of received data in accordance with High Level Data Link Control Procedure is disclosed. When the byte length of an information field included in the received data, for example, is detected, initial data determined based on the byte length is generated from initial data generation circuit. A counting device, after being initialized by the initial data, starts counting operation in response to detection of a start flag. When a stop flat is detected, the counting device stops the counting operation, and the data counted at the time represents the byte length of the information field. Since an adder/subtracter is not necessary to detect the byte length, time required for the detection can be shortened.

Data length detection device for detecting length of frame data defined

A signal generator for generating pulse signals having a waveform required by the Recommendation of International Telegraph and Telephone Consultative Committee (CCITT) is disclosed. The signal generator utilizes two D/A converters whereby the limitation of the operable frequency of the D/A converters restricts the variation rate of the output pulses. Each D/A converter provides the converted analog signal to the pulse transformer at timings different from one another. The pulse transformer detects the difference between the provided analog signals and provides a pulse signal having the required waveform. The difference of the output voltages between the two D/A converters varies at two times the operable frequency rate of the D/A converters, resulting in the pulse signals changing at a rate exceeding the operation frequency of the D/A converters.

Signal generator for generating pulse signals having particular

There are disclosed an FCS encoder responsive to data to be transmitted for generating a frame check sequence (FCS) code to check a transmission error, and an FCS decoder for detecting an error. These FCS encoder and FCS decoder have a division circuit and a multiplication circuit each of which comprises shift registers in 16 stages and EXOR gates. Since there is no need for logical elements to be connected between the respective shift registers, this FCS encoder can be constituted to show a regular circuit layout on a semiconductor substrate.

Error check code generating device and transmission error detecting

A bus circuit comprises a bus interconnection (1) and a plurality of local bus interconnections (10). A plurality of circuit blocks (21a to 21d) are connected to each of the plurality of local bus interconnections (10). A multiplexer (70), a bus driver (60) and a transmitting circuit (80A) are provided corresponding to each of the local bus interconnections (10). Each multiplexer (70) selects one of the outputs from the corresponding plurality of circuit blocks (21a to 21d) and applies the selected one to the bus driver (60). The bus driver (60) drives the bus interconnection (1) according to the output of the multiplexer (70). The local bus interconnections (10) are precharged to a predetermined potential in advance. When any of the plurality of transmitting circuits (80A) is selected, the selected transmitting circuit (80A) either discharges the corresponding local bus interconnection (10) or holds the same at a predetermined potential according to the information on the bus interconnection (1).

Bus circuit and operating method thereof

A communication control processor for storing own data being set respectively for plural data links, and parameters related thereto or address of the other memory in which the parameters related to the data link are stored, in a CAM and address accessed by retrieval of the CAM, respectively. By retrieving the CAM according to the own data of the data link, the parameters related to the data link are to be read, updated, or cleared.

Communication control processor

A content addressable memory device capable of correct retrieval operation comprises a flag bit column (12) provided in a memory cell array. The flag bit column (12) stores a flag signal indicating whether a word is in a data written state or an empty state for each word in a data array (2). In the retrieval operation, the data written in the data array (2) and a flag bit column (12) are simultaneously retrieved, providing a correct retrieval result. In addition, since the flag bit column (12) is provided in the memory cell array, it can be controlled in a manner similar to controlling the data array (2).

Content addressable memory with flag storage to indicate memory state

A first comparator compares a voltage of a pair of primary terminals of a pulse transformer with a first reference voltage, to apply an output voltage corresponding to the voltage difference therebetween to a gate of an N channel MOSFET. The N channel MOSFET is responsive to the output voltage for controlling current flowing through a primary side of a pulse transformer. Consequently, even if the impedance of a load connector to a pair of secondary terminals of the pulse transformer is fluctuated, a voltage between the pair of secondary terminals is kept constant. A second comparator compares the output voltage of the first comparator with a second reference voltage, to apply an output voltage corresponding to the voltage difference therebetween to a gate of a P channel MOSFET. When the load impedance becomes low, the P channel MOSFET performs control such that the output voltage of the second comparator does not exceed a predetermined value. Consequently, current flowing through the primary side of the pulse transformer is limited not to exceed a constant value. Thus, a voltage between output terminals does not exceed a constant value.

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Hyogo, Japan

Takeo Nakabayashi