Renesas Electronics Corporation

Nec Electronics Corporation

Nec Corporation

Takehiro Ueda

Hiroshi Kawaguchi

Yasuhiro Okamoto

Norio Okada

Takashi Aoki

A semiconductor device includes an aluminum layer, a passivation film, and a protective film arranged between the aluminum layer and the passivation film. A plurality of aluminum regions are formed in the aluminum layer. A width of a gap between the adjacent aluminum regions is equal to or less than twice a thickness of the protective film. The gap is filled with the protective film

Semiconductor device with protective film for reducing aluminum slide in aluminum wiring and manufacturing method thereof

The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.

Semiconductor device having integrated turn-on and turn-off resistors and diode

A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.

Semiconductor device and manufacturing method thereof

The semiconductor device includes a first electrode, a second electrode electrically coupled to the first electrode, and a third electrodes electrically coupled to at least one of the first and the second electrode, a first plating deposition portion on the first electrode, a second and a third plating deposition portions formed on the second and the third electrode, respectively. The areas of the second and the third plating deposition portion are smaller than the area of the first plating deposition portion. The periphery length of the third plating deposition portion is longer than the periphery length of the second plating deposition portion.

Semiconductor device with electrode plating deposition

Semiconductor device includes an element region in which the semiconductor element is provided, a semiconductor substrate including an outer peripheral region surrounding the element region, a plurality of semiconductor elements provided in an array-like in the element region. The element region includes a main circuit region in which the main circuit of semiconductor device is formed, and a sense circuit region in which a sense circuit for measuring the drain current flowing through the semiconductor element of the main circuit region is formed. Semiconductor element of the sense circuit region is surrounded by other semiconductor elements. Sense circuit region is covered with a main circuit source electrode which is connected to the semiconductor element of the main circuit region.

Semiconductor device

A high-electron-mobility transistor has a buffer layer, a channel layer, a barrier layer, a mesa-shaped cap layer, a source electrode formed on one side of the cap layer, a drain electrode formed on the other side, and a gate electrode formed over the cap layer via a gate insulating film. The semiconductor device has an element isolation region defining an active region in which the semiconductor device is provided. The gate electrode extends from over the active region to the over the element isolation region. In plan view, the active region has a projection part projected to the direction of the element isolation region in a region overlapped with the gate electrode. By providing the active region with a projection part, the channel length of a parasitic transistor can be increased, and turn-on of the parasitic transistor can be suppressed.

Semiconductor device and method of manufacturing semiconductor device

Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part.

A high side transistor is coupled between a high potential side power source node and an intermediate node, and a recirculation diode is coupled between a low potential side power source node and the intermediate node, thereby forming a recirculation path when the high side transistor is OFF. A power source supply line couples the high potential side power source node with one end of the high side transistor. A surge recirculation device causes a current to flow in one direction, and a surge recirculation line couples the one end of the high side transistor to the high potential side power source node through the surge recirculation device, and causes a surge generated at the one end of the high side transistor to recirculate toward the high potential side power source node.

Switching device with surge recirculation device and surge recirculation line

A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Semiconductor device having a fuse element

A semiconductor device includes a semiconductor substrate and an electrical fuse formed on the semiconductor substrate, and including a first conductor and a second conductor electrically separated from the first conductor. In a state of the electrical fuse after a cutting processing, the first conductor is cut and separated into a first part electrically separated from the second conductor and a second part including a flowing region from which a material constituting the first conductor flows outward and which is electrically connected to the second conductor.

Semiconductor device, method of cutting electrical fuse, and method of determining electrical fuse state

A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region.

Method of manufacturing a semiconductor device including concave portion

A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

A semiconductor device includes a transistor that has a trench formed in an element forming region of a substrate, a gate insulating film formed on side faces and a bottom face of the trench, a gate electrode formed on the gate insulating film so as to bury the trench, a source region formed on one side in the gate longitude direction, which is formed on the surface of the substrate, and a drain region formed on the other side in the gate longitude direction. Here, the gate electrode is formed so as to be exposed also on the substrate outside the trench, and the gate electrode is disposed so as to cover upper portions of both ends of the trench and so as to form at least one concave portion having a depth reaching the substrate in a center portion.

Growing community of inventors

Kanagawa, Japan

Takehiro Ueda