Nippondenso Co., Ltd.

Denso Corporation

Takayuki Sugisaka

Toshio Sakakibara

Shoji Miura

Makio Iida

Makoto Ohkawa

Satoshi Shiraki

Yasuaki Tsuzuki

Ichiro Ito

Akito Fukui

Atsumi Takahashi

Tomio Yamamoto

Hiroyuki Ban

Hiroshi Tanaka

Mitsuhiro Saitou

Tadashi Shibata

Atsushi Komura

Tadashi Suzuki

Osamu Ishihara

Akitaka Murata

Shuichi Ito

An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.

Method of etching metallic thin film on thin film resistor

When a barrier metal disposed on a thin film resistor material is wet-etched to expose the underlying thin film resistor material as a thin film resistor, the wet etching is performed at first and second steps. The first step is performed using H O /NH OH solution, and is stopped before the thin film resistor material is exposed. Then, the second step is performed using H O /H O solution until the thin film resistor material is exposed with a desired length, thereby forming the thin film resistor.

Method of processing metal and method of manufacturing semiconductor device using the metal

A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.

Design for a semiconductor device having elements isolated by insulating

A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.

High withstand voltage type semiconductor device having an isolation

A trench isolation junction type SOI semiconductor device which reduces substrate warpage while suppressing increase in production steps and a method for producing the same are disclosed. A junction substrate is formed by bonding a semiconductor substrate having an outer insulation film on a non-junction main surface with a semiconductor layer with an inner insulation film sandwiched therebetween. After forming a silicon nitride film as a mask for the purpose of forming a trench in the semiconductor layer, silicon nitride film accumulated on the outer insulation film is removed. By doing this, warpage of the semiconductor substrate due to discrepancies in the thermal expansion rates of the rigid silicon nitride film and semiconductor substrate can be prevented. In a junction type SOI semiconductor device formed via the method, an outer insulation film of identical thickness and identical density to an inner insulation film is formed on a non-junction main surface (i.e., rear surface) of a semiconductor substrate. By doing this, warpage of the semiconductor substrate can be prevented.

SOI semiconductor device and method of producing same wherein warpage is

A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.

Dielectric isolated type semiconductor device provided with bipolar

A dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process is provided. High-concentration regions are formed as active regions on a surface portion of an islandish semiconductor region which is isolated from an adjacent semiconductor region by means of an isolation trench. According to a first aspect of the present invention, an N type crystalline defect suppression region doped at a high concentration and deeper than the high-concentration regions is formed over the entire surface of an adjacent semiconductor region. According to a second aspect of the present invention, a high-concentration N type crystalline defect suppression region is provided on a surface portion of a P type high-concentration region is formed with identical structure and by an identical production process. By means of these N type regions, crystalline defects are reduced.

Dielectric isolated type semiconductor device

Method for fabrication of semiconductor device

A semiconductor device is provided in which a contact is very simply formed on conductive material for capacitive coupling prevention. Two silicon substrates are bonded through a silicon oxide film. And a trench extending to the silicon oxide film is formed in one of silicon substrates so as to isolate between plural circuit elements from each other, and islands for circuit element formation are compartmently formed by the trench. A silicon oxide film is formed on an outer periphery portion of the islands for circuit element formation. Furthermore, an island for capacitive coupling prevention is formed by the silicon substrate between the islands for circuit element formation and is applied thereto to be maintained in an electric potential of constant.

Growing community of inventors

Okazaki, Japan

Takayuki Sugisaka