Sony Corporation

Takayuki Gomi

Hiroyuki Miwa

Katsuyuki Kato

Hiroaki Ammo

Takashi Noguchi

Shigeru Kanematsu

Hiroaki Anmo

Hirokazu Ejiri

Norikazu Ouchi

Tomotaka Fujisawa

Mamoru Shinohara

Minoru Nakamura

Koji Kobayashi

Hideki Mori

Akio Kayanuma

Norikazu Ohuchi

Norikazu Chuchi

In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N-type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.

Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate

A logic circuit is formed of an I L cell structure in which a difference of switching speeds at every collectors in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constant current source transistor and a switch transistor is formed on a common semiconductor substrate, a first semiconductor layer ( ) doped with a first conductivity type impurity and a second semiconductor layer ( ) doped with a second conductivity impurity are electrically isolated from each other on a semiconductor substrate. A plurality of collector electrodes of the switch transistor and a plurality of collector regions ( ) based on diffusion of impurity are formed by the second semiconductor layer ( ). The first semiconductor layer ( ) includes a base electrode deriving portion, and a direct contact portion which directly contacts with the semiconductor substrate between a plurality of collector regions ( ). An external base region ( ) is formed by diffusion of first conductivity type impurity from the direct contact portion.

Integrated injection logic semiconductor device and method of fabricating the same

A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is formed by high-energy ion implantation prior to formation of the n,type buried collector region of the vertical NPN transistor, and a p,type buried collector region of the vertical PNP transistor is formed subsequently to formation of an n-type epitaxial layer and a device separating region is formed in the n-type epitaxial layer whereby the thickness of the n-type epitaxial layer is optimized to a required minimum value. A method for producing a semiconductor device is also provided in which a first vertical bipolar transistor of a first conductivity type and a second vertical bipolar transistor of a second conductivity type, electrically isolated from each other, are formed on a semiconductor substrate having a pre-set conductivity type. A buried collector region of the second vertical collector region is formed before formation of a buried collector region of the first vertical transistor.

Bipolar transistor device and method for manufacturing the same

A semiconductor device comprises: a substrate; a first buried layer of a first conduction type formed in the substrate; a second buried layer of the first conduction type formed in the substrate; a third buried layer of the first conduction type formed in the substrate; an epitaxial layer of the first conduction type formed on the substrate; a well region of a second conduction type formed in the epitaxial layer above the third buried layer; source/drain regions of the first conduction type formed in the well region; a first base region of the second conduction type formed in the epitaxial layer above the first buried layer; a first impurity region of the first conduction type formed on the first base region; a second base region of the second conduction type formed in the epitaxial layer above the second buried layer; a second impurity region of the first conduction type formed on the second base region; a first lead-out layer of the first conduction type connected to the first buried layer; and a second lead-out layer of the first conduction type connected to the second buried layer. The second buried layer has an impurity concentration substantially equal to that of the third buried layer.

Semiconductor device

A logic circuit is formed of an I.sup.2 L cell structure in which a difference of switching speeds at every collector in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constant current source transistor and a switch transistor is formed on a common semiconductor substrate, a first semiconductor layer (13) doped with a first conductivity type impurity and a second semiconductor layer (19) doped with a second conductivity impurity are electrically isolated from each other on a semiconductor substrate. A plurality of collector electrodes of the switch transistor and a plurality of collector regions (20) based on diffusion of impurity are formed by the second semiconductor layer (19). The first semiconductor layer (13) includes a base electrode deriving portion, and a direct contact portion which directly contacts with the semiconductor substrate between a plurality of collector regions (20). An external base region (17) is formed by diffusion of first conductivity type impurity from the direct contact portion.

Integrated injection logic semiconductor device

In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N.sup.+ -type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.

Method of making plurality of bipolar transistors

In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic base layer 12 to each other, and at least a part of a base layer 6 of the second bipolar transistor are formed simultaneously with each other, and then the link base layer 5 in a region where the intrinsic base layer 12 will be formed is removed by an etching treatment, and then by a selective epitaxial growth method, the intrinsic base layer 12 is formed in the region where the link base layer 5 is removed.

Method of manufacturing heterojunction bipolar device having Si.sub.1-x

A semiconductor device includes a heterojunction bipolar transistor and a junction gate type field effect transistor which are formed on a semiconductor base. A base region and graft base regions of the heterojunction bipolar transistor, and a channel region and source/drain regions of the junction gate type field effect transistor, are formed of a first semiconductor layer of a first conduction type. The first semiconductor layer is formed of mixed crystals of silicon-germanium which has a higher carrier mobility than silicon. An emitter region of the heterojunction bipolar transistor and a gate region of the junction gate type field effect transistor are formed of a second semiconductor layer of a second conduction type which makes a heterojunction with the first semiconductor layer.

Heterojunction bipolar semiconductor device

A process for forming a first bipolar transistor having a single polysilicon structure and a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor on the same substrate. In the process of fabricating a semiconductor device in which a first bipolar transistor having a single polysilicon structure, a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor, and a third bipolar transistor having a double polysilicon structure are provided on the same semiconductor substrate, a base contact portion of the first bipolar transistor and an emitter of the second bipolar transistor are formed in the same step, and an emitter of the first bipolar transistor and base contact portions of the second and third bipolar transistors are formed in the same step.

Process of fabricating semiconductor device

A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is formed by high-energy ion implantation after formation of the n.sup.+ type buried collector region of the vertical NPN transistor, and a p.sup.+ type buried collector region of the vertical PNP transistor is formed subsequently to formation of an n-type epitaxial layer and a device separating region whereby the thickness of the n-type epitaxial layer is optimized to a required minimum value. A method for producing a semiconductor device is also provided in which a first vertical bipolar transistor of a first conductivity type and a second vertical bipolar transistor of a second conductivity type, electrically isolated from each other, are formed on a semiconductor substrate having a pre-set conductivity type. A buried collector region of the second vertical collector region is formed before formation of a buried collector region of the first vertical transistor.

A mesa bipolar transistor comprising a collector layer formed on a surface of a substrate, a base layer disposed on the substrate so as to be joined to the collector layer, an emitter layer disposed on the base layer is further provided with a sub base layer comprising at least one of a polysilicon layer containing impurities, a metallic silicide, and a diffused layer formed on the surface of the substrate and being disposed under or on the external base region which is a region of the base layer lateral to that under the emitter layer so that the thickness of the external base region is increased to provide high conductivity.

Mesa bipolar transistor with sub base layer

A process of fabricating a semiconductor device includes the steps of: forming a base layer of a bipolar transistor (NPN bipolar transistor) on a semiconductor base body by selective epitaxial growth; and forming a dielectric film of a MIS capacitor on the same semiconductor base body. In this process, when side walls for isolating a base electrode connected to the base layer from an emitter layer formed on the base layer are formed, the dielectric film is formed of a silicon nitride film which is the same as one of films constituting the side walls. Thus, a MIS capacitor can be thus formed on one substrate together with a bipolar transistor only by adding the minimum number of steps to the steps of forming the bipolar transistor.

Process of fabricating integrated heterojunction bipolar device and MIS

A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Manufacturing method for making bipolar device having double polysilicon

A method of producing a bipolar transistor includes the step of forming an emitter contact layer containing a high concentration of impurity by means of plasma doping or solid-state diffusion without causing diffusion of impurity in a base layer. This makes it possible to realize a thin base layer having a high impurity concentration. The invention also provides a method of producing a semiconductor device including a bipolar transistor and another device element such as a resistor element including a polysilicon layer containing an activated impurity in such a manner that both the bipolar transistor and the device element are disposed on the same single substrate, the method including the steps of: forming a polysilicon layer containing an activated impurity on the surface of a substrate; and then forming a base layer of the bipolar transistor. This method prevents the base layer from being affected by heat treatment on the polysilicon layer.

Method of producing Si-Ge base heterojunction bipolar device

To form NPN and PNP transistors on the same base for example to obtain a complementary bipolar transistor it has been necessary to make an epitaxial layer a thick film, and this has resulted in deterioration of the characteristics of the NPN transistor. Also, because a step of forming an alignment mark has been necessary this has increased the number of manufacturing steps needed to make a complementary bipolar transistor. This invention provides a semiconductor device manufacturing method which solves this problem as follows: After a first opening 13 (alignment mark 16) and a second opening 14 are formed in an insulating film 12 formed on a semiconductor base 11 and a doping mask 15 is then formed on the semiconductor base 11, a third opening 17 is formed thereon with the alignment mark 16 as a reference. After an impurity 18 is introduced into the semiconductor base 11 through the third opening 17, the doping mask 15 is removed and after that an impurity 19 is introduced into the semiconductor base 11 by solid-phase diffusion through the second opening 14 and a first embedded diffusion layer 20 is thereby formed and at the same time the impurity 18 is caused to diffuse and form a second embedded diffusion layer 21. Then, after an epitaxial layer is formed, an impurity diffusion layer is formed therein by ion injection (not shown).

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Tokyo, Japan

Takayuki Gomi