Fujitsu Corporation

Fujitsu Microelectronics Limited

Takatoshi Deguchi

Satoshi Takechi

Akihiko Otoguro

A semiconductor device manufacturing method for suppressing surface roughness of a Low-k insulating film during etching. In a laminated structure comprising a layer having formed thereon a lower copper wiring, a SiC film and a SiOC film, a via and an upper copper wiring are formed as follows. The SiOC film is etched to form a via hole opening that reaches the SiC film and then to form wiring grooves that communicate with the opening. Thereafter, when the SiC film on the bottom of the opening is etched to form a via hole, a deposited film of etching products is formed on surfaces of the via hole and the wiring grooves. This deposited film allows planarization of the SiOC film surface, which is exposed to plasma, formed thereon the via hole and the wiring grooves. Subsequently, formation of a Ta film and burying of plating copper are performed.

Manufacturing method for semiconductor device

The present invention provides a method of manufacturing a semiconductor device which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more. It also provides a method of forming a pattern which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more.

Method of manufacturing semiconductor device and method of forming pattern

After forming an SiNfilm as a hard mask for a wiring, a lower resin film for filling and planarizing a level difference thereon is formed. Next, an SOG film is formed on the lower resin film, and a resist mask on which a via hole pattern is formed is formed thereon. The SOG film is etched by using the resist mask as a mask. The lower resin film is etched by using the SOG film as a mask, and at the same time, the resist mask is removed. Then, a triple layer hard mask is etched by using the lower resin film as a mask. Consequently, a via hole pattern is formed on these films, and the SOG film is simultaneously removed. According to this method, the resist mask having a pattern as designed can be obtained, and a micro pattern with high precision can be obtained.

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Kawasaki, Japan

Takatoshi Deguchi