Fujitsu Corporation

Fujitsu Microelectronics Limited

Fujitsu Semiconductor Limited

Takashi Saiki

Hiroyuki Ohta

Hiroyuki Kanata

Hiroshi Nomura

Kenichi Okabe

Hidenobu Fukutome

Youichi Momiyama

Yuka Hayami

Akira Yamanoue

Tsunehisa Sakoda

Junji Oh

Kengo Inoue

Masataka Kase

Toshifumi Mori

Ryou Nakamura

Katsuaki Okoshi

Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.

Method of fabricating field effect transistors with different gate widths

Field effect transistors with different gate widths

An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.

Semiconductor device and method of fabricating the same

A silicon nitride film having a thickness of 3 nm or less is formed on the surfaces of a P-well and N-well, as well as on the upper and side surfaces of a gate electrode, in which the silicon nitride film can be formed, for example, by exposing the surface of the P-well and N-well, and the upper and side surfaces of the gate electrode to a nitrogen-gas-containing plasma using a magnetron RIE apparatus. Then, pocket layers, extension layers and source/drain layers are formed while leaving the silicon nitride film unremoved.

Semiconductor device and method of manufacturing thereof

An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.

Method of suppressing diffusion in a semiconductor device

A dose of arsenic for an extension region in an NMOS transistor is in a range from 5&#xd7;10to 2&#xd7;10ions/cmand preferably in a range from 1.1&#xd7;10to 1.5&#xd7;10ions/cm. Also, in addition to arsenic, a low concentration of phosphorus is doped into the extension region by ion implantation. Consequently, with a semiconductor device of the CMOS structure, it is possible to prevent unwanted creeping of silicide that occurs often in the shallow junction region depending on a concentration of an impurity having a low diffusion coefficient as represented by arsenic. Further, not only can the resistance in the shallow junction region be lowered, but also an amount of overlaps can be optimized in each transistor.

Semiconductor device

Method of manufacturing a semiconductor device with a notched gate electrode

The semiconductor device comprises a silicon wafer, a multilayer interconnectionburied in inter-layer insulation film formed on the upper surface of the silicon wafer, and a silicon nitride filmwhich is formed on the back surface of the silicon waferand is an insulation film having a tensile stress, relaxing a stress exerted to the silicon waferby the inter-layer insulation films in which the multilayer interconnectionis buried.

Semiconductor device and method for fabricating the same

A semiconductor device manufacture method has the steps of: (a) forming a polishing stopper layer over a semiconductor substrate; (b) etching the semiconductor substrate to form a trench; (c) forming a first liner insulating layer of silicon oxide over the surface of the trench; (d) forming a second liner insulating layer of silicon nitride over the first liner insulating layer, the second liner insulating layer having a thickness of at least 20 nm or at most 8 nm; (e1) depositing a third liner insulating layer of silicon oxide over the second liner insulating layer by plasma CVD at a first bias; and (e2) depositing an isolation layer of silicon oxide by plasma CVD at a second bias higher than the first bias, the isolation layer burying a recess defined by the third liner insulating layer.

Manufacture of semiconductor device having STI and semiconductor device manufactured

The semiconductor device fabrication method comprises the step of forming electrodesin a first element regionand in a second element region; the step of forming a first resist filmwhich is opened in the first element region; the step of forming a first dopant diffused regionwith the first resist filmand the gate electrodeas a mask; the first ashing processing step of ashing the first resist film; the step of forming a sidewall insulation filmover the side wall of the gate electrode; the step of forming a second resist filmwhich is opened in the first element region; the forming a second dopant diffused regionwith the second resist film, the gate electrodeand the sidewall insulation filmas a mask; and the second ashing processing step for ashing the second resist film. The ashing processing period of time in the first ashing processing step is shorter than the ashing processing period of time in the second ashing processing step.

Growing community of inventors

Kawasaki, Japan

Takashi Saiki