Semiconductor Components Industries, LLC

Sanyo Electric Co., Ltd.

Murata Manufacturing Co., Ltd.

Sanyo Semiconductor Co., Ltd.

Kanto Sanyo Semiconductor Co., Ltd.

Kanto Sanyo Semiconductors Co., Ltd.

Takashi Noma

Hiroyuki Shinogi

Michael John Seddon

Yusheng Lin

Kazuo Okada

Shinzo Ishibe

Katsuhiko Kitagawa

Yukihiro Takao

Hiroshi Yamada

Francis J Carney

Yuichi Morita

Akira Suzuki

Yasuyuki Morishima

Yoshinori Seki

Noboru Okubo

Mitsuru Okigawa

Noboru Kato

Eiji Kurose

Shigeki Otsuka

Iwao Fukushi

Keiichi Yamaguchi

Hisao Otsuka

Takayasu Otagaki

Nobuyuki Takai

Ryoji Tokushige

Hideaki Yoshimi

Tomoaki Nishi

Motoaki Wakui

Tatsuya Ando

Masanori Iida

Kazuhiro Saito

Gordon M Grivna

Nobuo Ikemoto

Jun Adachi

Nobuhito Tsubaki

Hiroshi Takemura

Hisashi Akiyama

George Chang

Yoshihiko Nishizawa

Kosuke Yamada

Hiroshi Kanamori

Naoyuki Yomoda

Hideyuki Inotsume

Koichi Kuhara

Kuniaki Yosui

Jun Sasaki

Keiichi Ichikawa

Hirokazu Yazaki

Takahiro Sumi

Takayuki Tsukizawa

Jun Urakawa

Tetsuya Ikeda

Keito Yonemori

Takeshi Miki

Hidehiko Sugimoto

Ryu Shimizu

Takanori Tsuchiya

Takayuki Kaida

Koji Kamada

Hisayoshi Uchiyama

Hiromitsu Hongo

Kyoji Toshinari

Katsu Horikoshi

Kimihide Saito

Tetsuya Miwa

Masahiro Maruki

Ken Takakura

Ryo Kawai

Yoichi Kanuma

Shunsuke Yasuda

Ichiro Yamawaki

Yoshihiro Kubota

Masaji Hara

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

Semiconductor package electrical contact structures and related methods

A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.

Multi-chip system-in-package

Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.

Semiconductor package electrical contacts and related methods

Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.

Substrate alignment systems and related methods

In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Fan-out wafer level packaging of semiconductor devices

Implementations of a semiconductor package may include a semiconductor die including a first side and a second side where the first side of the semiconductor die includes one or more electrical contacts; a layer of metal coupled to the second side of the semiconductor; and a stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts.

Semiconductor package stress balance structures and related methods

Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

Thinned semiconductor package and related methods

A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

Semiconductor wafer and method of ball drop on thin wafer with edge support ring

Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.

Semiconductor device with backmetal and related methods

A method for making an integrated passive device (IPD) die includes grinding a backside of a semiconductor substrate to reduce a thickness of a central portion of the semiconductor substrate while leaving a mechanical support ring on an outer portion of the substrate, and forming a through-substrate via (TSV) from the backside of the substrate. The TSV defines interconnect access to at least one passive component embedded in an insulator material disposed on a front surface of the semiconductor substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.

Integrated passive device and fabrication method using a last through-substrate via

According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.

Isolation in a semiconductor device

Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

Structures for aligning a semiconductor wafer for singulation

Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street.

Backside metal photolithographic patterning die singulation systems and related methods

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Ota, Japan

Takashi Noma