Hitachi, Ltd.

Elpida Memory, Inc.

Hitachi Vlsi Engineering Corp.

Other

Sega Enterprises, Ltd.

Takashi Nishida

Tokuo Kure

Eiji Takeda

Takashi Hashimoto

Toshiaki Yamanaka

Koichiro Ishibashi

Hideo Todokoro

Shoji Shukuri

Hiroyasu Shichi

Akihiro Shimizu

Yoshio Sakai

Atsuo Watanabe

Naotaka Hashimoto

Katsuhiro Kuroda

Yoshifumi Kawamoto

Yasuhiro Mitsui

Takahiro Nagano

Kazushige Sato

Ken Ninomiya

Masahito Hiroshima

Shimpei Iijima

Yoshimi Sudo

Shuji Ikeda

Toshihiko Tanaka

Norio Hasegawa

Katsutaka Kimura

Yoshinobu Nakagome

Digh Hisamoto

Masataka Minami

Kenji Sato

Satoshi Meguro

Kazuyoshi Oshima

Shinichiro Kimura

Katsuhiro Shimohigashi

Takahiro Daikoku

Yoshio Homma

Osamu Tsuchiya

Aritoshi Sugimoto

Toshiaki Masuhara

Osamu Minato

Toru Kaga

Kozo Watanabe

Saburo Nonogaki

Atsushi Hiraiwa

Fumiyuki Kobayashi

Takumi Ueno

Nobuyuki Moriwaki

Nobuaki Hayashi

Hiroshi Shiraishi

Katsuro Sasaki

Akira Masaki

Minoru Yamada

Kuninori Imai

Shoji Hanamura

Kiyonori Ohyu

Nobuo Kotera

Masakazu Yamamoto

Keiichirou Nakanishi

Takao Iwayanagi

Seiki Harada

Atsushi Saiki

Sadayuki Nakano

Tetsu Oi

Yasuhiro Sugawara

Shigeru Honjo

A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle of each mask pattern so as not to expose parts of wafer, the aperture of the wafer becomes nearly cocoon-shaped with a constriction in the middle. Thereby, the peripheral length of the aperture can be increased without changing the occupation rate of the mask patterns in a cell. Further, the shape of the bottom of the aperture also becomes nearly cocoon-shaped with a constriction in the middle, and therefore it is possible to increase the mechanical strength of cylinders.

Semiconductor device and manufacturing method thereof

A rubber composition containing (A) an ethylene-&agr;-olefin based copolymer rubber having an intrinsic viscosity &lsqb;&eegr;&rsqb; of 2.0-10.0 as determined in xylene at 70&deg; C., (B) a softening agent, and (C) a filler, which composition is superior in heat resistance and fatigue resistance, is obtained by a process including the steps of dividing component (A) into portions (A ) and (A ), dividing component (B) into portions (B ) and (B ), dividing component (C) into portions (C ) and (C ), kneading portions (A ), (B ) and (C ) together to obtain a first blend, adding portions (A ), (B ) and (C ) to the first blend to obtain a second blend and kneading the second blend to obtain the rubber composition.

Process for producing rubber composition and rubber composition

Image processing method and electronic device

An X-ray analyzing method for inspecting opening states of fine holes comprises the steps of: irradiating a finely converged electron beam into a first fine hole, observing an X-ray emitted from the inside of said first fine hole in order to obtain an first X-ray analysis data about the residue substance existing at the bottom of said first fine hole; irradiating a finely converged electron beam into a second fine hole, observing an X-ray emitted from the inside of said second fine hole in order to obtain an second X-ray analysis data about the residue substance existing at the bottom of said second fine hole; and comparing said first X-ray analysis data with said second X-ray analysis data, forming a judgment as to whether or not a difference between said first and second analysis data is smaller than a predetermined threshold value and using an outcome of said judgment to determine the opening states of said first and second fine holes. The X-ray observations are carried out by detecting only the X-rays emitted within the angular range -.theta. to +.theta. where notation .theta. is an angle formed with a center axis of the irradiated electron beam and so defined that tan .theta. is equal to a/d whereas notations a and d are the radius and the depth of the fine holes.

Method and apparatus for X-ray analyses

An X-ray analyzing method includes the steps of applying an irradiated electron beam, converged by a condenser lens and an objective lens into a thin beam, to the inside of a fine hole existing on the surface of a sample; observing X-rays generated from a residual substance existing inside the fine hole; and performing a qualitative and quantitative analysis of the residual substance. The X-rays are observed by an X-ray detector installed in an internal space of the condenser lens, an internal space of the objective lens, or between the condenser lens and the objective lens, by detecting only the X-rays radiated within the angular range -.theta. to +.theta., where .theta. is an angle formed with a center axis of the electron beam, and so defined that tan .theta. is substantially equal to a/d, where a and d are the radius and the depth of the fine hole, respectively.

Method and apparatus for x-ray analyses

A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.

Method of fabricating bipolar transistor having high speed and MOS

An arrangement is provided to decrease the junction degradation caused by the leakage current at a p-n junction in semiconductor devices. This arrangement can be useful for a variety of devices, and is especially effective for reducing junction degradation at the source or drain region of a MOSFET. To achieve such a reduction, a p-n junction layer is provided at a p-n junction of a semiconductor region and a substrate. Carrier concentration distributions of a p-type layer and an n-type layer of the p-n junction layer are set so that an electric field which tends to be increased by a local electric field enhancement in a depletion layer of the p-n junction due to a precipitate introduced from a semiconductor surface will not exceed 1 MV/cm. When the depth of a depletion layer of the p-type layer or the n-type layer is referred to as Xp or Xn, and the slope of the carrier concentration, Ap or An, the following relation is provided:

Semiconductor device including arrangement for reducing junction

There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Semiconductor memory device having static random access memory

The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.

Semiconductor device having a low-resistivity planar wiring structure

A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

Semiconductor memory device having flip-flop circuits

A semicondcutor device and a manufacturing method thereof are disclosed in which higher integration can be achieved without increasing the total manufacturing steps. The semiconductor device includes at least two MOS transistors having the same channel types, the gate electrodes of which are constructed of polycrystal silicon layers which contain an impurity, and a bipolar transistor, the base electrode of which is constructed of a polycrystal silicon layer which contains and impurity. In particular, the respective gate electrodes of the two MOS transistors contain impurities of different conductivity types from one another.

Semiconductor device

A semiconductor device having a CMIS structure for forming a static random access memory is disclosed which device can increase the packing density of the memory and reduce the stand-by power thereof. In this semiconductor device, a first MISFET of a first conductivity type is formed on and a substrate, a second MISFET of a second conductivity type is formed over the first MISFET with a first insulating film therebetween to form a stacked CMIS structure. The second MISFET is made up of a first conductive film, a second insulating film and a second conductive film, with the source, drain and channel regions of the second MISFET being formed in the first conductive film. A first resistive drain region is formed between the channel and drain regions of the first conductive film so that an impurity of the second conductivity type is contained in the first resistive drain region at a lower concentration than in the drain region, or the first resistive drain region is substantially undoped. The first resistive drain region is disposed over the gate electrode of the first MISFET, and the gate insulating film and gate electrode of the second MISFET are formed of the second insulating film and the second conductive film, respectively. In a case where a semiconductor memory device having a static random access memory cell which is provided with a flip-flop circuit of the stacked CMIS type, is formed, a pair of first MISFET's and a pair of third MISFET's of the first conductivity type are formed on the substrate, and the second MISFET is formed on one MISFET of the first MISFET's and the third MISFET's.

Semiconductor memory devices having stacked polycrystalline silicon

This invention relates to a radiation-sensitive composition having resistance to oxygen reactive-ion etching and a process for forming a pattern by using the same. The radiation-sensitive composition of this invention comprises a mixture of cis-(1,3,5,7-tetrahydroxy)-1,3,5,7-tetraphenylcyclotetrasiloxane and a polysilsesquioxane, said mixture containing 5 to 100 wt. % of cis-(1,3,5,7-tetrahydroxy)-1,3,5,7-tetraphenylcyclotetrasiloxane, and a resist containing a phenolic resin soluble in an aqueous alkali solution.

Radiation-sensitive resist composition with an admixture of

A method of manufacturing a semiconductor device. An insulation film having an opening is formed on a semiconductor substrate. The opening is filled with an electrically conductive material so as to substantially flatten the top surface of the opening filled with an electrically conductive material, an intermediate layer of an electrically conductive material having a greater allowable current density than that of a wiring layer to be formed thereon is formed so as to cover at least their surface of the electrically condictive material deposited in the opening. Subsequently, the wiring layer is formed so as to extend from the surface of the intermediate layer onto the surface of the insulation film. A semiconductor device incorporating the wiring layer having an extremely high reliability can be easily realized.

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Tokyo, Japan

Takashi Nishida