Fujitsu Corporation

Powerchip Technology Corporation

Powerchip Corporation

Powerchip Semiconductor Corporation

Takashi Miida

Akira Takei

Riichiro Shirota

Hideki Arakawa

Yoshihiko Hika

Ching Sung Yang

Tzung Ling Lin

Kiyoshi Tashiro

In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

Programming method for NAND flash memory device to reduce electrons in channels

An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel electrodes, and a transparent conductive layer covering the photo conductive layer.

Image sensor and fabrication method thereof

An image sensor includes charge storage regions which gradually store charges corresponding to the amount of light received, a plurality of image transfer elements which gradually transfer the charges, and transfer gates which transfer the charges in the charge storage regions to the charge transfer elements. The image sensor provides further a device which changes an electric potential of an electrode of the charge storage regions in accordance with the amount stored of the charges, and a device which detects the electric potential of the electrode and outputs the detected electric potential as a switchover timing control signal of the transfer gates.

Image sensor

A nonvolatile semiconductor memory device including at least one memory cell which comprises a floating-gate, a control gate and a single impurity diffusion region formed exclusively for the memory cell. In this device, a small depletion region and a large depletion region due to the charged and discharged state of the floating-gate represent the information '1' and '0'.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device of a floating-gate type comprises a floating-gate and two control gates. The floating-gate is divided into two conductive regions having a conductivity type opposite to each other. A first control gate is placed above a first region and a second control gate is placed above a second region. In this device, the erase operation is performed by causing avalanche breakdown within the floating-gate.

Growing community of inventors

Tokyo, Japan

Takashi Miida