Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Takashi Kuroi

Katsuyuki Horita

Maiko Sakai

Katsuomi Shiozawa

Hidekazu Oda

Hirokazu Sayama

Maiko Kobayashi

Yoshinori Okumura

Yasuyoshi Itoh

Tomohiro Yamashita

Shigeki Komori

Masashi Kitazawa

Masato Ishibashi

Masahiro Shimizu

Satoshi Shimizu

Shigeru Kusunoki

Shuichi Ueno

Masahide Inuishi

Masayoshi Shirahata

Takehisa Yamaguchi

Shuuichi Ueno

Syuichi Ueno

Yasuo Inoue

Takaaki Tsunomura

Chikayoshi Morishima

Hiromichi Kobayashi

Katsuomi Siozawa

Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.

Semiconductor device and manufacturing method thereof

To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer.

Semiconductor device and its manufacturing method

In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.

A substrate surface (S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (S) in an active region is exposed. An oxide film () is thereby provided. An exposed substrate surface (S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film () is epitaxially grown on the exposed substrate surface (S). Thereafter the silicon film () is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film () in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.

Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate

A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.

Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same

In a trench ( ), an oxynitride film ( ON ) and a silicon oxide film ( O ) are positioned between a doped silicon oxide film ( D) and a substrate ( ), and a silicon oxide film ( O ) is positioned closer to the entrance of the trench ( ) than the doped silicon oxide film ( D). The oxynitride film ( ON ) is formed by a nitridation process utilizing the silicon oxide film ( O ). The vicinity of the entrance of the trench ( ) is occupied by the silicon oxide films ( O O ) and the oxynitride film ( ON ).

Semiconductor device with element isolation using impurity-doped insulator and oxynitride film

A substrate surface ( S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface ( S) in an active region is exposed. An oxide film ( ) is thereby provided. An exposed substrate surface ( S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film ( ) is epitaxially grown on the exposed substrate surface ( S). Thereafter the silicon film ( ) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film ( ) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.

A semiconductor device less susceptible to inverse narrow channel effect and its manufacturing method are provided. A silicon nitride film ( ) is adopted as element isolation regions; the silicon nitride film ( ) has a smaller etch rate than a sacrificial silicon oxide film ( ) which serves as a sacrificial layer during ion implantation ( ). This prevents formation of recesses in the silicon nitride film ( ) during the removal of the sacrificial silicon oxide film ( ), which weakens the strength of the electric fields at the gate edges. Weakening the strength of the electric fields at the gate edges suppresses the inverse narrow channel effect, so that the MOS transistor offers a characteristic closer to a characteristic in which the threshold voltage keeps a constant value independently of the channel width. Thus an MOS transistor having a good characteristic can be manufactured.

A technique for preventing a decrease in alignment accuracy during a photolithography process is provided. A substrate ( ) is prepared, in the surface ( ) of which trenches ( ) for use as alignment marks and trenches ( ) each forming an element isolation structure are formed and on the surface ( ) of which a polysilicon film ( ) is formed, avoiding the trenches ( ). The trenches ( ) are filled with an insulation film ( ). The insulation film ( ) is then selectively etched to partially remove the insulation film ( ) in the trenches ( ) and to leave the insulation film ( ) on side and bottom surfaces ( ) of the trenches ( ). Using the insulation film ( ) in the trenches ( ) as a protective film, the polysilicon film ( ) is selectively etched. The use of the insulation film ( ) in the trenches ( ) as a protective film prevents the substrate ( ) from being etched and thereby prevents the shape of the trenches ( ) from being changed. This results in prevention of a decrease in alignment accuracy during a photolithography process.

Method of manufacturing semiconductor device

A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure ( ) formed on a main surface of a semiconductor substrate ( ). A pair of extensions ( ) and source/drain regions ( ) are selectively formed in the main surface so as to face each other through a channel region ( ), a silicon oxide film ( ) is formed on the trench-type element isolation structure ( ) and on the source/drain regions ( ) through a silicon oxide film ( ), sidewalls ( ) are formed on sides of the silicon oxide film ( ), a gate insulating film ( ) is formed on the main surface in a part where the channel region ( ) is formed and a gate electrode ( ) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls ( ) and the upper surface of the gate insulating film ( ).

Semiconductor device including inversely tapered gate electrode and manufacturing method thereof

An SRAM of the present invention comprises a plurality of memory cells, which are formed over a plurality of wells, which store data and which do not have a well contact region for fixing the potential of the wells, and a plurality of well contact cells for fixing the potential of the wells that are formed over the plurality of wells so as to adjoin the memory cells, wherein the areas of the memory cells and the areas of the well contact cells are equal.

Static-type semiconductor memory device

Two source/drain regions ( ) belonging to separate elements which are adjacent to each other are connected through a metal layer ( ) having the same height as a height of a metal layer ( ) forming a part of a gate electrode. In a manufacturing process, an insulating layer ( ) is made of other material than and inserted between two insulating layers ( ) and ( ). The two insulating layers ( ) and ( )function as molds for burying the metal layers ( ), ( ) and ( ) therein and made of the same material. The metal layer ( ) can therefore be formed at the same height as the height of the metal layer ( ). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.

Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer

A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N -type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.

Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P -type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.

Semiconductor device and method of fabricating the same

There is provided a method of forming an element isolation structure that can maintain its element isolation capability even with the progress of miniaturization of semiconductor elements. Through thermal processing in a nitrogen atmosphere at 900&deg; C., a non single-crystal silicon film ( ) is crystallized into single-crystal form by epitaxial growth on the main surface of a substrate, thereby to form an epitaxial silicon film ( ). The epitaxial silicon film ( ) is then planarized by CMP to expose the upper surface of an element isolation insulating film ( ). This completes the element isolation insulating film ( ) having a two-level protruding shape.

Growing community of inventors

Tokyo, Japan

Takashi Kuroi