Texas Instruments Corporation

Nippon Sanso Corporation

Hitachi, Ltd.

Takashi Inui

Akihiro Nakamura

Kiyoshi Nakai

Yukihide Suzuki

Takushi Ohsaki

Kiyotaka Okuzawa

Shunichi Sukegawa

Yoshihiro Ogata

Tomohiro Suzuki

Masayoshi Hayashida

Akira Wakaizumi

Shigeki Numaga

Kiyoshi Nakatsuka

Katsuyoshi Yanagita

Atsushi Naito

Hiroyuki Yoshida

Seiichi Yamamoto

Tadayoshi Iwasaki

Yasuo Tatsumi

Toshiya Miyagawa

Mitsuo Kigure

Hiroshi Taira

Ryuichi Yazaki

Kohsuke Ikeda

Toshiyuki Ishiuchi

Masahide Matsumoto

Nobuyasu Tomita

Satoshi Sawaguchi

Hiroyuki Miyake

Fusao Nakamura

A halogen treatment is conducted comprising: a halogenation step wherein a halogenation heat treatment for preparing a halogenated carbonized charcoal is conducted in which the carbonized charcoal is brought into contact with halogen; and a dehalogenation step wherein a dehalogenation treatment is conducted in which a part of or all halogen atoms in the halogenated carbonized charcoal are eliminated. A porous carbonaceous material is obtained at a high yield, and the amounts of nitrogen, oxygen, carbon dioxide, and methane adsorbed by this porous carbonaceous material are large. When this porous carbonaceous material is used as an electrical double layer capacitor carbon, the electrostatic capacity is increased compared to conventional carbonaceous materials. Consequently, a carbonaceous material is obtained which has micopores and/or sub-micropores which are suitable for the adsorption of small molecules such as nitrogen, and for storage of electrochemical energy.

Porous carbonaceous material, manufacturing method therefor and use thereof

The objective is to provide a type of dynamic memory which does not adversely affect the data, even when noise is superimposed on the RAS signal.

Dynamic memory

A carbonaceous material for an electrical double layer capacitor is produced by performing a halogenation treatment step wherein a halogenated dry-distilled charcoal is obtained by bringing a dry-distilled charcoal into contact with a halogen gas; a molding treatment step of adding a binding agent to the halogenated dry-distilled charcoal to form a molded article; and a dehalogenation treatment step wherein a part or all of the halogen in the molded article is eliminated. The carbonaceous material for an electrical double layer capacitor obtained by this method is impregnated with sulfuric acid to form a carbon electrode for an electrical double layer capacitor. This electrode is used to form an electrical double layer capacitor.

Manufacturing method for carbon material for electrical double layer

A circuit is designed with a memory array (102) having a plurality of memory cells arranged in rows and columns (204, 206, 210, 212). The memory array has a plurality of bit line pairs (202, 208, 282, 284) with each bit line pair connected to a respective column of memory cells and a bit line reference terminal (254). A control circuit (700) produces a control signal, the control signal having a first voltage for a first time, a second voltage for a second time and a third voltage for a third time. A precharge circuit (350, 352) connects at least one bit line pair to the bit line reference terminal, responsive to the first voltage for the first time and the second voltage for the second time. The precharge circuit disconnects the at least one bit line pair from the bit line reference terminal, responsive to the third voltage for the third time.

Bit line precharge circuit with reduced standby current

Carbon for a lithium secondary battery, lithium secondary battery, and

Carbon adsorbent, manufacturing method therefor, gas separation method

An input circuit for a memory address bit operates at high operating speed. A PMOS transistor 112 is provided between a supply line for 1/2V.sub.CC and a node N11. When not in operation, node N11 of input portion 11A is precharged not to the power supply voltage V.sub.CC, but to 1/2V.sub.CC, a potential halfway between the power supply voltage V.sub.CC and 0 V. Another PMOS transistor 117 is provided between a PMOS transistor 111 and node N11 of the input stage to prevent leakage between V.sub.CC and 1/2V.sub.CC. As a result, an enable signal ENB goes to a high level, the circuit enters the operating state, address bit signal Ai is input, and the time needed to shift the level of node N11 to V.sub.CC or 0 V becomes short.

Address bit latching input circuit

A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.

Semiconductor memory device having plural memory mats with centrally

A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory device can be shortened, and the power consumption can be cut. In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

Semiconductor memory device

A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.

Word line driving circuit

A dynamic random access memory device has a memory cell array which includes a first memory cell array part and a second memory cell array part portioned in a first direction parallel with the bit lines, a plurality of column switches, one provided for each of the bit lines, a plurality of input/output lines each connected to different ones of the bit lines via associated ones of the column switches, a row address decoder for decoding a first portion of an address signal and a column address decoder for decoding a second portion of the address signal to thereby simultaneously access at least two memory cells with the address signal. The input/output lines extend in a second direction parallel with word lines and are divided into first and second groups of input/output lines connected to those bit lines which belong to the first and second memory cell array parts, respectively in which the first input/output line group is isolated from the second input/output line group. A first input/output gate circuit is connected to the first group of input/output lines and a second input/output gate circuit is connected to the second group of input/output lines, in which the first and second input/output gate circuits serve to selectively transfer therethrough, between main amplifiers and the first input/output line groups, data to be simultaneously read from or written into the at least two memory cells in the memory cell array.

Dynamic random access memory device having first and second I/O line

A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory/device can be shortened, and the power consumption can be cut. In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

A driving circuit for providing a predetermined voltage as a driving signal to a respective word line in a dynamic random access memory in a short time. The driving circuit includes an operation signal supply circuit portion for providing an operation signal, a driving signal output circuit portion which receives the operation signal and provides a driving signal as an output, and a voltage supply circuit portion for providing a predetermined voltage to the driving signal output circuit portion in producing the driving signal. A bipolar switching element is provided in the driving signal output circuit portion to control the voltage supply from the voltage supply circuit portion and responds to the operation signal to provide the voltage from the voltage supply circuit portion as the voltage producing the driving signal in a short time.

Driving circuit for providing a voltage boasted over the power supply

Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data. Upon decoding the serial sequence selection data of the partial address buffer, a plurality of MOS transistors included in the selector portion are rendered conductive in sequence in response to respective control signals applied to the gates thereof to connect the plurality of data registers via their output buffers to respective output drivers in a sequence determined by the decoded selection data of the partial address buffer for serial data output in the selected serial data output sequence.

Data selector circuit and method of selecting format of data output from

A sense amplifier circuit is described for switching plural inputs at high speed. At least two transistors for providing at least two true input signals are connected in parallel and have their source terminals connected to a common node from which an output signal may be read. Similarly, at least two other transistors for providing the inverse of the true input signals are connected in parallel and their source terminals are connected to another common node from which an inverse of the output signal may be read. The common nodes are then precharged to the same voltage. True and inverse input signals are applied to their respective transistors through transfer gates where all the true input signals are greater than their respective inverse signals. Therefore, the on-resistance of each of the transistors to which a true input is applied have a higher on-resistance than the associated transistors to which an inverse input is applied. Current flow then rapidly decreases through the transistors transmitting the inverse input signal as current is switchably applied to the transistors transmitting the true input signals.

Growing community of inventors

Tsuchiura, Japan

Takashi Inui