Mitsubishi Denki Kabushiki Kaisha

Hitachi Metals, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Proterial, Ltd.

Fujitsu Corporation

Sony Interactive Entertainment Inc.

Takashi Hayasaka

Shigeki Ohbayashi

Toshihiko Hirose

Masayuki Iketani

Setsu Kondo

Yoshiyuki Fujino

Detian Huang

Toru Sumi

Ryohei Okada

Tamotsu Sakurai

Takeshi Usami

Kazumasa Yanagisawa

Toshio Yamada

Hiromitsu Kuroda

Shohei Hata

Tomoshi Futatsuya

Hiroshi Bando

Kazuya Nishi

Yoshio Takazawa

Minoru Takatsuto

Satoshi Yajima

Yasushi Sugaya

Hiroyuki Yamamoto

Miki Onaka

Atsushi Ohba

Manabu Nishizawa

Taku Ogura

Yoshikazu Miyawaki

Seigi Aoyama

Kensaku Ishizuka

Kiyotoshi Noheji

Keisuke Fujito

Masanori Kondoh

Togo Fukushi

Shinichi Mizoguchi

A copper alloy wire is composed of a copper alloy including indium of 0.3 mass % or more and 0.65 mass % or less, and has 0.2% proof stress of 300 MPa or more, electrical conductivity of 80% IACS or more, and elongation of 7% or more.

Copper alloy wire, plated wire, electric wire and cable using these

A method for manufacturing a conductive wire includes conducting a continuous casting of a conductive alloy material at a casting rate of not less than 40 mm/min and not more than 200 mm/min to form a conductive wire with a primary diameter, the conductive alloy material containing not more than 1.0 mass % of an added metal element, reducing a diameter of the conductive wire with the primary diameter to form a conductive wire with a secondary diameter, heat treating the conductive wire with the secondary diameter so that tensile strength thereof is reduced to not less than 90% and less than 100% of tensile strength before the heat treating, and reducing a diameter of the conductive wire with the secondary diameter and the reduced tensile strength to generate a logarithmic strain of 7.8 to 12.0 therein to form a conductive wire with a tertiary diameter.

Conductive wire, method for manufacturing conductive wire, casting conductive wire, cable and method for manufacturing cable

A copper alloy wire is made of a copper alloy, and the copper alloy contains indium, a content of which is equal to or more than 0.3 mass % and equal to or less than 0.45 mass %. A tensile strength of the copper alloy wire is equal to or higher than 800 MPa, and an electrical conductivity of the same is equal to or higher than 80% IACS.

Copper alloy wire, plated wire, electrical wire and cable

A wire rod made of an aluminum alloy. The aluminum alloy includes Al crystal grains, an Al&#x2014;Zr compound, and an Al&#x2014;Co&#x2014;Fe or Al&#x2014;Ni&#x2014;Fe compound. The aluminum alloy includes high-angle tilt crystal grain boundaries, each of which has a difference between crystal orientations in both its sides of 15 degrees or more, and low-angle tilt crystal grain boundaries, each of which has a difference between crystal orientations in both its sides of 2 degrees or more and less than 15 degrees. An average grain diameter of ones of the Al crystal grains surrounded by the high-angle boundaries is 12 &#x3bc;m or more. An average grain diameter of the ones of the Al crystal grains surrounded by the high-angle boundaries, ones of the Al crystal grains surrounded by the high-angle boundaries and the low-angle boundaries, and ones of the Al crystal grains surrounded by the low-angle boundaries, is 10 &#x3bc;m or less.

Aluminum alloy wire rod and producing method therefor

An alloying-element additive for adding an alloy element to a copper melt formed by melting a base material including a copper in manufacturing a copper alloy. The alloying-element additive includes a wire-shaped or plate-shaped core including an alloy element, and an outer layer material including a copper and covering the core. A weight ratio of the copper in the outer layer material and the alloy element in the core is in a range of weight ratio where the alloying-element additive has a liquid phase in a temperature range of not more than a melting point of the copper in a copper-alloy element phase diagram.

Alloying-element additive and method of manufacturing copper alloy

An aluminum alloy wire rod has a chemical composition consisting of 0.1 to 1.0 mass % of Co, 0.2 to 0.5 mass % of Zr, 0.02 to 0.09 mass % of Fe, 0.02 to 0.09 mass % of Si, 0 to 0.2 mass % of Mg, 0 to 0.10 mass % of Ti, 0 to 0.03 mass % of B, 0 to 1.00 mass % of Cu, 0 to 0.50 mass % of Ag, 0 to 0.50 mass % of Au, 0 to 1.00 mass % of Mn, 0 to 1.00 mass % of Cr, 0 to 0.50 mass % of Hf, 0 to 0.50 mass % of V, 0 to 0.50 mass % of Sc, 0 to 0.50 mass % of Ni, the balance being Al and inevitable impurities, and a metal structure including Al crystal grains, an Al&#x2014;Co&#x2014;Fe compound and an Al&#x2014;Zr compound. The Al crystal grains having a crystal grain diameter of 10 &#x3bc;m or less have an area ratio of 90% or more. The wire rod has a tensile strength of 150 MPa or more, an electrical conductivity of 55% IACS or more and when heated at 200 deg C. for 10 years, a strength of 90% or more of its initial state strength.

Aluminum alloy wire rod and producing method thereof

Method for manufacturing a conductive wire

An information processing apparatus according to embodiments includes: a comment acquisition unit for acquiring a comment of a viewer for a program from an external posting site to which a comment, which is feedback on the content of a program, is instantly posted; and a comment displaying unit for displaying the comment acquired by the comment acquisition unit in a live information display area located below an image display screen for displaying an image of the program. The comment displaying unit scroll-displays, in a horizontal direction, a comment acquired by the comment acquisition unit in either a first lane or a second lane of the live information display area.

Viewer interface for broadcast image content

A Raman amplifier inputs pump light into an optical fiber (transmission path) through which an optical signal passes, to amplify the optical signal. An optical receiving unit is provided downstream of the Raman amplifier and monitors the power of the optical signal amplified by the Raman amplifier. A calculating unit determines Raman amplification gain based on the power of the optical signal monitored by the optical receiving unit, and calculates the power of a noise component included in the optical signal based on the gain. The calculating unit, in real-time, calculates the power, which varies in complicated manners depending on conditions, and outputs information concerning to the power to another apparatus at a frequency on the order of milliseconds.

Optical amplification apparatus, optical communication apparatus, and optical communication method

There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Semiconductor integrated circuit and testing method thereof

A method of erasing data of a nonvolatile semiconductor memory unit includes the first step of collectively applying a preliminary write pulse to memory transistors, the second step of repeating, up to a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse, the third step of repeating, up to a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse, the fourth step of repeating, up to a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse and the fifth step of repeating a selective recovery operation on the memory transistors until the memory transistors are not in an overerased state.

Method of erasing data of nonvolatile semiconductor memory unit

Particular blocks are a boot block and parameter block having a storage capacity smaller than that of a general block. In the case where a boot block is not required, a signal BOOTE is set at an L level. In the case where a signal BLKSEL is at an H level in an erasure mode, a control unit selects four blocks aligned in a horizontal direction at the same time. The control unit also selects two blocks simultaneously in the vertical direction. As a result, the particular eight blocks are selected. The boot block and parameter block can be erased collectively as one block having a capacity similar to that of a general block. Therefore, a flash memory corresponding to the case of including a boot block and not including a boot block can be implemented simultaneously with one chip. Thus, the designing and fabrication process can be simplified.

Non-volatile semiconductor memory device that can be fabricated with erasure unit modified

At the time of writing data, a tester outputs a chip enable signal /CE of the L level and selection signals of the L level to simultaneously make semiconductor memory devices active. At the time of reading data, the tester outputs the chip enable signal of the L level to the semiconductor memory devices, and selectively switches the logic level of a selection signal to be outputted to some semiconductor memory devices and that of the selection signal to be outputted to the other semiconductor memory devices to the L level. In such a manner, a number of semiconductor memory devices can be tested without increasing the number of pins of the tester.

SEMICONDUCTOR MEMORY DEVICE WHICH CAN BE SIMULTANEOUSLY TESTED EVEN WHEN THE NUMBER OF SEMICONDUCTOR MEMORY DEVICES IS LARGE AND SEMICONDUCTOR WAFER ON WHICH THE SEMICONDUCTOR MEMORY DEVICES ARE FORMED

A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

Static semiconductor memory device having improved characteristics

Growing community of inventors

Tokyo, Japan

Takashi Hayasaka