Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Takanori Hirota

Takeshi Oshita

Atsuhiko Ishibashi

Yasushi Hayakawa

Masato Suzuki

Masashi Ishii

Yoshiyuki Ota

Koichiro Mashiko

Kimio Ueda

Yoshiki Wada

A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit N times and a second pulse outputted from the pulse generation circuit.

Semiconductor device

A semiconductor device is provided which can reduce a parasitic inductor and/or parasitic capacitance added to the wiring that couples spiral inductors and MOS varactors included in a VCO. An LC-tank VCO includes first and second spiral inductors, and first and second MOS varactors. As seen perpendicularly to the semiconductor substrate, the first and second MOS varactors are arranged in a region between the first spiral inductor and the second spiral inductor.

A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Clock data recovery circuit capable of generating clock signal synchronized with data signal

Assuming that clocks in an A clock driver (), a B clock driver () and a CMOS buffer circuit () have delay values Ta, Tb and Td, respectively, a delay value Ta&#x2212;Td is stored in a register circuit () when terminals '0' of selector circuits () are selected, and a delay value Ta&#x2212;Td&#x2212;Tb is stored in a register circuit () when the terminals '0' are switched to &#x201c;1&#x201d;. Thus, determining a delay value at the CMOS buffer circuit () allows a phase difference between the A clock driver () and B clock driver () to be determined.

Semiconductor integrated circuit for phase management of clock domains including PLL circuit

In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption. Further, with positional relation between the body contact regions (9), (10) and the gate contact regions (5), (7), the device is capable of freely setting the transistors to be of either a gate control type or a gate fixed type. As a result, the gate array type semiconductor device achieves high-speed operation and low power consumption.

Gate array semiconductor device

A level conversion circuit as a semiconductor integrated circuit has a first load resistance (R1), a second load resistance (R2), a first NMOS transistor (MN3) and a second NMOS transistor (MN4) connected to them (R1 and R2) in parallel, respectively, that are driven directly by positive CMOS level signals, a first bipolar transistor (Q1), and a second bipolar transistor (Q2). Both emitters of the first and second bipolar transistors (Q1 and Q2) are connected commonly, and a voltage potential that is lower than a voltage potential of a collector of the first bipolar transistor (Q1) by a predetermined voltage potential is supplied into a base of the second bipolar transistor (Q2).

Growing community of inventors

Tokyo, Japan

Takanori Hirota