Kabushiki Kaisha Toshiba

Takamichi Kasai

Hideo Kato

Nozomi Kasai

Hiroshi Watanabe

Takahiro Suzuki

Akira Umezawa

Yasuhiko Honda

Akihiro Yamazaki

Kiyomi Naruke

Kazuaki Isobe

Yoshiharu Hirata

Shinya Fujisawa

Hiroyuki Sasaki

Hideyoshi Takai

Ryu Hondai

Yuji Komine

According to one embodiment, a nonvolatile semiconductor storage device includes a first well region of a first conductivity type, a second well region of the first conductivity type, a third well region of a second conductivity type, a bit line and a column decoder. A first cell array including a plurality of memory cells is formed in the first well region. A second cell array including a plurality of memory cells is formed in the second well region. The third well region includes the first and second well regions. The bit line is connected to the memory cells included in the first cell array and the memory cells included in the second cell array. The column decoder is connected to the bit line.

Nonvolatile semiconductor storage device with multiple well regions and a shared bit line

A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit.

Non-volatile semiconductor storage device with address search circuit used when writing

A semiconductor memory deviceis proposed including an internal address generation circuit, a first internal address control signal generation part, a second internal address control signal generation part, and an internal address control signal selection circuithaving an OR gate transistor. The internal address generation circuitgenerates an internal address signal based on input address data. The first internal address control signal generation partgenerates a first internal address control signal and having a function which fixes the first internal address control signal at a predetermined level with the elapse of a fixed period of time. The second internal address control signal generation partgenerates a second internal address control signal corresponding to an input of a predetermined command. The OR gate transistortransmits either the first internal address control signal or the second internal address control signal to the internal address generation circuit

Semiconductor memory device

A nonvolatile semiconductor memory includes a cell array, redundancy array, erase circuit, timer, and controller. The cell array has a plurality of memory cells. The redundancy array has a plurality of redundant cells capable of replacing the memory cell. The erase circuit performs an erase operation on a target cell including the memory cell or the redundant cell. The timer measures the time elapsed from the start of the erase operation performed for the target cell by the erase circuit. The controller stops the erase operation and replaces the target cell with the redundant cell, when detecting that a predetermined time has elapsed from the start of the erase operation by the measurement of the elapsed time by the timer.

Nonvolatile semiconductor memory including redundant cell for replacing defective cell

In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold values at a given level or more, erasing the cells to set their threshold values at a lower level or less, executing weak programming once on a cell whose threshold value is lower than a further lower level, by applying a lower voltage to the cell, repeating the weak programming on the cell when its threshold value is still lower than the further lower level, until the value reaches the further lower level or more, verifying whether a cell is present whose threshold value is higher than the lower level, and returning the processing to the processing of setting the threshold values of the cells at the lower level or less, when verifying that the above cell is present.

Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device

This invention provides a nonvolatile semiconductor memory device capable of avoiding complicatedness of algorithm for normal write operation and a write operation prior to erasing in a memory system in which the distribution of threshold of cells after erasing is adjusted. This nonvolatile semiconductor memory device generates check bits as error correction code according to a check bit generating matrix so formed that in both the normal write operation and the write operation prior to erasing, the factors of &ldquo;1&rdquo; of respective rows satisfy the quantity absolutely necessary for generating check bits and the quantity of the factors of &ldquo;1&rdquo; is an odd number.

Error correcting circuit for making efficient error correction, and involatile semiconductor memory device incorporating the same error correcting circuit

The invention provides a flash memory having a security function and a protect function. When the release of the security function has been instructed, all data stored in each block of a flash memory main body is forcibly erased, ignoring the setting of the protect function. After that, the security function is released, thereby enabling readout of data. This being so, even if a third person releases the security function, leakage of data to the outside can be prevented.

Nonvolatile semiconductor memory device with security function and protect function

The present invention relates to a method of rewriting data in a microcomputer additionally provided with a flash memory having a refresh mode, in which the data retained in an area arbitrarily specified in the flash memory is transferred to a RAM for temporary evacuation and after the data in the area has been erased, the data evacuated to the flash memory is written into the area again.

Growing community of inventors

Yokohama, Japan

Takamichi Kasai