Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubushi Denki Kabushiki Kaisha

Mitsubhishi Denki Kabsuhiki Kaisha

Takahiro Tsuruda

Hideto Hidaka

Katsuhiro Suma

Kazutami Arimoto

Fukashi Morishita

Takeshi Fujino

Mitsuya Kinoshita

Tetsushi Tanizaki

Mako Kobayashi

Teruhiko Amano

Masaki Tsukude

Shigeki Tomishima

Kazuyasu Fujishima

Tadashi Nishimura

Tadato Yamagata

Hiroshi Kimura

Masakazu Hirose

Shigehiro Kuge

Akira Hosogane

A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Semiconductor memory device including an SOI substrate

A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.

Semiconductor device using an SOI substrate

A program data latch circuit supplies one of a write bit line potential and a write prohibiting potential corresponding to multilevel data to be written, to a bit line in accordance with a level of a write control signal in a write operation. On the other hand, a program sense latch circuit compares a threshold value of a memory cell transistor sensed through the bit line with a reference potential, changes the level of the write control signal if the threshold value becomes a value corresponding to the multilevel data and instructs output of the write prohibiting potential in a verification operation.

Nonvolatile semiconductor memory device capable of writing multilevel data at high rate

The present invention provides a non-volatile semiconductor memory device including a sector selecting circuit. When a non-defective sector is designated by an address signal, a spare decoder outputs a signal such that a NAND gate can select the non-defective sector, when a defective sector is designated by the address signal, the spare decoder outputs a signal for activating an alternate non-defective sector, and when the alternate non-defective sector is designated by the address signal, a signal for making all of a plurality of sectors non-selective. As a result, it is possible to reduce a defective rate of the non-volatile semiconductor memory device.

Non-volatile semiconductor memory device having a low defective rate

In the data writing sequence, judgement of writing is divided into two stages of judgement and judgement In the judgement it is determined whether the data writing has been completed for at least one of a plurality of memory cells, and in the judgement it is determined whether the data writing has been completed for all the memory cells. Changing the writing conditions for the judgements and enables judgement of the data writing in an early stage.

Non-volatile semiconductor memory device with writing sequence enabling early-stage judgement of writing

A semiconductor memory device includes an SOI substrate, a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells and a plurality of body fixing lines. The plurality of word lines are disposed in the row direction on the SOI substrate. The plurality of bit line pairs are disposed in the column direction on the SOI substrate. The plurality of memory cells are located on the SOI substrate and each are disposed correspondingly to one of crossings between the plurality of word lines and the plurality of bit line pairs. Each of the plurality of memory cells includes a capacitor and a transistor. The transistor is connected between the capacitor and one bit line in the corresponding bit line pair. The transistor is turned on in response to the potential of the corresponding word line. The plurality of body fixing lines are disposed on the SOI substrate. The plurality of body fixing lines are supplied with a predetermined potential. The transistors in the plurality of memory cells have source regions, drain regions and body regions located between the source and drain regions. The body regions of the transistors in the plurality of memory cells are connected to the plurality of body fixing lines.

Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions

A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.

Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area

A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.

Semiconductor memory device

A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.

Growing community of inventors

Hyogo, Japan

Takahiro Tsuruda