Hitachi, Ltd.

Renesas Technology Corp.

Other

Takahiro Onai

Katsuyoshi Washio

Tohru Nakamura

Masatada Horiuchi

Kazuhiro Ohnishi

Takeo Shiba

Fumio Ootsuka

Kiyoji Ikeda

Shinichi Saito

Nobuyuki Sugii

Yoichi Tamaki

Kazuyoshi Torii

Akihisa Uchida

Kazuo Nakazato

Mitsuo Nanba

Shoji Wakahara

Shuji Ikeda

Hideo Miura

Takayuki Kawahara

Digh Hisamoto

Toshiyuki Mine

Hiroyuki Ohta

Masayuki Miyazaki

Natsuki Yokoyama

Tokuo Kure

Hiroshi Masuda

Tomonori Tanoue

Yuji Yatsuda

Yasushi Goto

Katsumi Ogiue

Ryuta Tsuchiya

Toshifumi Takeda

Tetsuya Hayashida

Katsuya Oda

Katsuhiko Ichinose

Yukihiro Kumagai

Tadashi Arai

Takashi Uchino

Eiji Ohue

Yukihiro Kiyota

Kunihiko Watanabe

Nakazato Kazuo

Masayoshi Saitoh

Taroh Inada

A light-emitting device according to the present invention includes a first electrode unit for injecting an electron, a second electrode unit for injecting a hole, and light-emitting units and electrically connected to the first electrode unit and the second electrode unit respectively, wherein the light-emitting units and are formed of single-crystal silicon, the light-emitting units and having a first surface (topside surface) and a second surface (underside surface) opposed to the first surface, plane orientation of the first and second surfaces being set to a (100) plane, thicknesses of the light-emitting units and in a direction orthogonal to the first and second surfaces being made extremely thin.

Silicon light emitting diode, silicon optical transistor, silicon laser and its manufacturing method

The present invention relates to an LSI in which functions can be changed, and realizes, particularly, a system LSI in which functions are changed by changing connections of the circuit by use of MEMS switches. A bistable MEMS switch which can maintain states, and exhibits optimal stitching property, i.e., the switch has a very small resistance of several &#x3a9; or less in an on-state, and has an infinite resistance in an off-state; is employed. An element in which functions can be changed during operation, is produced by utilizing a wiring layer of a CMOS semiconductor to form the MEMS switch. A semiconductor device exhibiting high-degree of freedom for changing functions, high-speed, and having small area, is realized.

Device and data processing method employing the device

In a miniaturized field effect transistor, the roughness of the interface between a gate dielectric film and a gate electrode is controlled on an atomic scale. The thickness variation of the gate dielectric film is lowered, whereby a field effect transistor with high mobility is manufactured. An increase in the mobility in the field effect transistor can be achieved not only in the case of using a conventional SiOthermal oxide film as the gate dielectric film but also in the case of using a high dielectric material for the gate dielectric film.

Semiconductor device and manufacturing thereof

Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer of a pocket structure, the device of the present invention is suppressed in fluctuations in the threshold voltage. Moreover, with a relative increase in the controllable width of a depletion layer, a sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve a switching rate of the MISFET.

Semiconductor device including impurity layer having a plurality of impurity peaks formed beneath the channel region

A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium

The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics. In a semiconductor device including an n-channel field effect transistorand a p-channel field effect transistor, a stress control filmcovering a gate electrodeof the n-channel field effect transistorundergoes film stress mainly composed of tensile stress. A stress control filmcovering a gate electrodeof the p-channel field effect transistorundergoes film stress mainly caused by compression stress compared to the filmof the n-channel field effect transistor. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics

Semiconductor device having a replacement gate type field effect transistor and its manufacturing method

A method of manufacture of a semiconductor device calls for forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer with a pocket structure, the device produced by the present method operates in such a way that fluctuations in the threshold voltage are suppressed. Moreover, with a relative increase in the controllable width of a depletion layer, the sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve the switching rate of the MISFET.

Method of manufacturing a semiconductor device having two peaks in an impurity concentration distribution

Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator

Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

Method of fabricating multi-layered structure having single crystalline

A self-aligned bipolar transistor which has a small base resistance and small emitter-base and collector-base capacitances and is operable at high speed is disclosed. This bipolar transistor is characterized in that a low concentration collector region made of single crystal Si--Ge is self-alignedly formed between an intrinsic base of single crystal Si--Ge and an intrinsic base, and that an extrinsic base electrode and an intrinsic base are connected only through a doped external base. With this arrangement, an energy barrier is not established at the collector base interface owing to the formation of the low concentration region of single crystal Si--Ge, so that the transit time of the carriers charged from the emitter is shortened. The connection between the intrinsic base and the extrinsic base electrode via the doped external base results in the reduction of the base resistance. In addition, the self-aligned formation of the emitter-base-collector leads to the reduction in capacitance between the emitter and the base and also between the collector and the base. Accordingly, a high-speed bipolar transistor can be realized and thus, circuits using the transistor are operable at high speed.

Heterojunction bipolar transistor

A hetero-junction bipolar transistor having an emitter composed of a semiconductor having a wider forbidden band width than that of a semiconductor constituting a base is disclosed. In the transistor, the emitter and the electrode leader area composed of a single crystalline semiconductor are provided being extended from the upper part of the emitter to the surface of the base through an insulating layer, for the purpose of making it possible to miniaturize the transistor and to operate the transistor at a high-speed by decreasing the emitter resistance.

Hetero-junction bipolar transistor and semiconductor devices using the

Multi-layered structure having single crystalline semiconductor film

A transistor is formed on a bonded SOI substrate. A collector electrode is connected to the peripheral sides of the collector areas on the insulator. A first insulator of isolation is formed on the peripheral side of the collector electrode. A base electrode is connected to a base area on the first insulator of isolation. Second insulators of isolation are formed on the peripheral side of a base electrode, and emitter electrode is connected to an emitter area by the second insulators of isolation. The connections between the collector electrode and the collector areas, between the base electrode and the base area, and between the emitter electrode and the emitter area are made under the emitter electrode, so the occupation area is small.

Semiconductor device

Growing community of inventors

Ome, Japan

Takahiro Onai