Kabushiki Kaisha Toshiba

Takahiro Hamano

Masataka Matsui

Mitsuo Isobe

Katsuhiko Sato

An address transition detecting circuit detects on address transition signal generated during the writing of input data into a static random access memory (SRAM) and generates an address detection signal as a monostable pulse of a predetermined length. A bit line precharge and equalize signals generating circuit generates, in synchronization with the address transition detection signal and an input signal on a write data line, a bit line precharge signal and bit line equalize signal which are supplied to their columns in memory. At a time of reading, the bit line precharge and equalize signals generating circuit supplies a high level potential to paired data lines to prevent a data entry from being made into the paired write data lines by a resetting operation. At a time of writing, a write data buffer circuit supplies complementary data to the paired write data lines and prevents a data signal entry from being made by a presetting operation onto the paired write data lines, for a predetermined period of time, in synchronization with the address transition detection signal. It is, therefore, possible to prevent an input signal entry for a predetermined period of time by a resetting operation and hence prevent a write error.

Semiconductor memory having an operation margin against a write recovery

A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line in response to an output from the NAND gate, a fuse element connected between the output terminal of the NAND gate and the input terminal of the inverter, and a MOS transistor connected between the input terminal of the inverter and a power supply voltage.

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Yamato, Japan

Takahiro Hamano