Rohm Co., Ltd.

Takaaki Fuchikami

Kiyoshi Nishimura

Hiromitsu Kimura

Yoshikazu Fujimori

Hiromi Uenoyama

Hideki Hayashi

Jun Muramoto

Takanori Ozawa

Noriyuki Shimoji

Kazuhisa Ukai

Hiroshi Sekiguchi

Hiroki Kato

Kohei Shoji

Masato Moriwake

Noriyuki Ema

Kazutaka Miyamoto

Disclosed is a semiconductor memory device including a memory cell based on a static random access memory having a 6T or 4T2R configuration and including a first internal node, a second internal node, a first ferroelectric capacitor, and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor having respective first ends connected respectively to the first internal node and the second internal node. For recovering data stored in a non-volatile fashion in the first ferroelectric capacitor and the second ferroelectric capacitor, a first access transistor connected between the first internal node and a first bit line and a second access transistor connected between the second internal node and a second bit line are turned on, and respective capacitive components of the first bit line and the second bit line are used as load capacitances.

Semiconductor memory apparatus

A data processing apparatus includes: a plurality of power supplies; a nonvolatile logic configured to be driven with power output from the plurality of power supplies; and a plurality of detection parts configured to detect output states of the plurality of power supplies, wherein the nonvolatile logic performs data processing based on a result of the detection of the plurality of detection parts.

Data processing apparatus, structure and power generation apparatus including the same

A counter includes: a count processing circuit including a nonvolatile register; a regulator receiving voltage from a direct current power supply, generating power supply voltage based on the received voltage for the count processing circuit, and supplying the power supply voltage to the count processing circuit; and a delay circuit receiving the power supply voltage and supplying a count signal to the count processing circuit after the power supply voltage is supplied to the count processing circuit. After having received the power supply voltage from the regulator, the count processing circuit updates a count value in response to the count signal and holds the updated count value in the nonvolatile register in a non-volatile manner.

Electronic circuit and electronic device including the same

Provided is a nonvolatile storage gate embedded logic circuit embedding a nonvolatile storage gate which can hold data after power supply cutoff and can cut off a power supply at the same time shifting into a standby state. The nonvolatile storage gate embedded logic circuit includes a logic calculation unit having a logic gate, and a nonvolatile storage gate having a nonvolatile storage element, a data interface control unit disposed so as to be adjoining to the nonvolatile storage element, and receiving a nonvolatile storage control signal for data read-out from the nonvolatile storage element and data write-in to the nonvolatile storage element, and a volatile storage element disposed so as to be adjoining to the nonvolatile storage element, receiving a data input signal and a clock signal, and outputting a data output signal.

Nonvolatile storage gate, operation method for the same, and nonvolatile storage gate embedded logic circuit, and operation method for the same

A data maintenance device includes: a first storage including volatile storage media; a second storage including nonvolatile storage media; an electronic circuit unit including at least one volatile register; and a selector configured to select one of the first and the second storage to be accessed by the electronic circuit unit. The selector selects the first storage in a state where data processing performed by the electronic circuit unit is ongoing, and the second storage in a state where the data processing is stopped for a shutdown of electric power of the data processing apparatus. The electronic circuit unit stores register data in the storage selected by the selector, the register data being stored in the register at the time when the data processing is stopped for the shutdown.

Data processing apparatus

A photoelectric conversion circuit includes: a photoelectric conversion element having one end to which bias voltage is applied and the other end from which photo current according to an amount of received light is output; and a photo current detecting unit clamping voltage of the other end of the photoelectric conversion element to a predetermined potential and detecting the photo current.

Photoelectric conversion circuit and solid state imaging device including same

An angular velocity signal detection circuit includes: a first current-voltage conversion circuit that converts, into a voltage, a current outputted from a first detection electrode of a gyroscope, and amplifies the voltage, thereby outputs a first conversion signal; a second current-voltage conversion circuit that converts, into a voltage, a current outputted from a second detection electrode of the gyroscope, and amplifies the voltage, thereby outputs a second conversion signal; an arithmetic operation unit that performs arithmetic operations by using the first conversion signal and the second conversion signal, and outputs a first processing signal and a second processing signal; and a third difference arithmetic operation circuit that amplifies a difference between the first processing signal and the second processing signal.

Angular velocity signal detection circuit and angular velocity signal detection method

By separately setting a capacitor on BL depending on whether the mode is a DRAM mode or an FRAM mode, it is compatible with improvement in a speed by BL capacitor reduction in the DRAM mode and a sufficient BL capacitance in the FRAM mode. A ferroelectric memory device includes: a plurality of bit lines BL disposed in a column direction; a plurality of word lines WL disposed in a row direction; a plurality of plate lines PL and a bit line capacitor control signal BLC; a ferroelectric memory cell () disposed at an intersection of the plurality of bit lines BL, the plurality of word lines WL, and the plurality of plate lines PL, and composed of a ferroelectric capacitor CF and a memory cell transistor QM; and a load capacitor adjustment cell () disposed at an intersection of the plurality of bit lines BL and the bit line capacitor control signal BLC, and composed of a load capacitor CL and a load capacitor adjustment transistor QL.

Ferroelectric memory device for adjusting the capacitor of a bit line

A voltage control circuit which can prevent the occurrence of imprint phenomenon is provided. In a voltage control circuit which applies voltage to a pair of electrodes including a first and a second electrode, a control unit switches the voltage applied to the pair of electrodes, in response to an operation mode of this circuit. In a normal mode, the control unit fixedly applies a first voltage to the first electrode and applies a data voltage of the first voltage or the second voltage to the second electrode, based on an instruction from the control unit. In an inversion mode, the second voltage is fixedly applied to the first electrode, and the data voltage of the first voltage or second voltage is applied to the second electrode. The control unit switches the mode between the normal mode and the inversion mode, in a predetermined cycle.

Voltage control circuit, voltage control method and light control apparatus utilizing the same

An organic EL element (Al) includes an anode () and a cathode () which are arranged opposite to each other, and an organic layer () intervening between the anode () and the cathode () and including a light emitting layer (). The cathode () is made of MgAg alloy and has a thickness of not more than 200 &#x212b;. Preferably, the thickness of the cathode () is in the range of 40 to 100 &#x212b;.

Organic el element, organic el display device, and process for producing organic el element

A ferroelectric memory device includes: a plurality of memory banks configured to include a memory cell array composed of a ferroelectric memory; a cache bank configured to be bus-connected with the memory banks, and for copying data stored in the memory banks; and a memory bank/cache control sequencer for accessing and refreshing to the memory banks and the cache bank, wherein a random access control to the ferroelectric memory is possible during each memory cycle without delay of refresh operation.

Ferroelectric memory device and operating method for the same

A data memory device is provided that is capable of reading data accurately even if the reading action is repeated. Respective output ends of memory cells D -D and input ends on one side of respective exclusive OR elements Eo -Eo are interconnected, and the output end of a polarity holding cell Dc and the input ends on the other side of the respective exclusive OR elements Eo -Eo are interconnected. When it is assumed that the stored value of the memory cell D is a logic &ldquo;1&rdquo; and the stored value of the polarity holding cell Dc is a logic &ldquo;0,&rdquo; the value of the output data Do read out becomes a logic &ldquo;1&rdquo;. By the reversal writing action that follows, the value of the memory cell D becomes a logic &ldquo;0&rdquo; and the stored value of the polarity holding cell Dc becomes a logic &ldquo;1.&rdquo; When the value of the memory cell D is read again in that state, the value of the output data Do is still a logic &ldquo;1.&rdquo; That is to say, even if data reading action is repeated, values of the output data Do -Do remain unchanged. However, the direction of polarization of respective ferroelectric capacitors constituting the memory cells D -D and the polarity holding cell Dc are reversed every time of the reading.

Data memory device

A semiconductor memory device including a memory element for storing data, and a supplemental element substantially electrically associated with the memory element at least at the time of reading data. The semiconductor memory device is for reading data stored in the memory element by applying specified electric action to the compound element including the memory element and the supplemental element substantially electrically mutually associated. The semiconductor memory device is characterized in that the electric characteristic of the supplemental element is adapted to be variable based on a signal for changing the electric characteristic of the supplemental element so that data may be read free from troubles.

Semiconductor memory device having a supplemental element for reading data stored in a memory element

An object of the present invention is to duplicate functions of a first device into a second device so as to have the same functions as the first device. CPU 23 supplies a predetermined input data to both the second device 19 and the first device 17. A plurality of logic data for generating output data correspond to specific input data are stored in the hard disk 26 as candidates. The CPU 23 selects a candidate which makes both the output data generated by the second device 19 and the first device 17 identical with each other for all the supplied input data within the candidates. The CPU 23 outputs a rewrite command to the second device 19 so as to execute logic data of the candidate thus selected. The output data of the second device 19 identical with the output data generated by the first device 17 can be obtained for all the supplied input data.

Device for duplicating functions and a method for duplicating functions

A switch SW 11 comprises a ferroelectric memory 26 and an AND gate 28. A data input line L11 and an output terminal of the ferroelectric memory 26 are connected to an input terminal of the AND gate 28. Also, output terminal of the AND gate 28 is connected to an AND input line L21. In order to write the switching data which switches the state of the switch SW11 either in open state or closed state into the ferroelectric capacitor 26, ferroelectric capacitors C11 and C12 are polarized in opposite directions with each other. The polarization is carried out in short period, and the polarization state can be maintained even when the power is turned off. So that, the switching data can be written repeatedly by changing direction of the voltage applied to the ferroelectric capacitors C11 and C12.

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Kyoto, Japan

Takaaki Fuchikami