International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Globalfoundries U.S. 2 LLC

Elpis Technologies Inc.

Globalfoudries Inc.

Tak H Ning

Alexander Reznicek

Jeng-Bang Yau

Jin Cai

Bahman Hekmatshoartabari

Pouya Hashemi

Karthik Balakrishnan

Kevin K Chan

Ghavam G Shahidi

Kangguo Cheng

Sufi Zafar

Devendra K Sadana

Davood Shahrjerdi

Ali Khakifirooz

Effendi Leobandung

Wilfried Haensch

Bahman Hekmatshoar-Tabari

Ning Li

Cheng-Wei Cheng

Kuen-Ting Shiu

Robert H Dennard

Christopher Peter D'Emic

Paul Michael Solomon

Jean-Olivier Plouchart

Daniel C Edelstein

Robert Dennis Miller

Kerry Bernstein

Marwan H Khater

Ramachandran Muralidhar

Wilbur David Pricer

Pranita Kulkarni

Dae-Gyu Park

Philip Joseph Oldiges

William J Cote

John Anthony Bracchitta

Brent A Anderson

Jack Allan Mandelman

Chung H Lam

Ali Afzali-Ardakani

Terence B Hook

Kenneth Parker Rodbell

Stephen McConnell Gates

Herbert Lei Ho

Zhen Zhang

Qiqing Christine Ouyang

Mahmoud M Khojasteh

Mark Charles Hakey

Michael S Gordon

Hemanth Jagannathan

Christian Lavoie

Oscar Van Der Straten

Amlan Majumdar

Pranita Kerber

Thomas M Shaw

Frank Robert Libsch

Deborah A Neumayer

Dieter F Wendel

James Douglas Warnock

Bipin Rajendran

K Paul Muller

Zhibin Ren

Ethan Harrison Cannon

Siegfried K Wiedmann

Robert B Laibowitz

Robert Rosenberg

Ko-Tao Lee

Leon Jacob Sigal

Lidija Sekaric

Can Bayram

Kam-Leung Lee

Ruilong Xie

Bruce Bennett Doris

Choonghyun Lee

John Atkinson Fifield

Bin Yang

Robert Russell Robison

Jeffrey Bowman Johnson

Alberto Valdes Garcia

Tze-Chiang Chen

Christos Dimitrios Dimitrakopoulos

Ahmet Serkan Ozcan

Jane M Shaw

Peter Juergen Klim

Chun-Chen Yeh

Jason D Hibbeler

James Spiros Nakos

Matthew Joseph BrightSky

Stanley Everett Schuster

Fadi Hikmat Gebara

Ching-Te Kent Chuang

Cherie Renee Kagan

Lloyd Andre Walls

Jeremy Daniel Schaub

Guann-Pyng Li

John Matthew Safran

Ronald Dennis Rose

Nicky C Lu

Narasipur G Anantha

Yulong Li

SangBum Kim

A Darlington pair sensor is disclosed. The Darlington pair sensor has an amplifying/horizontal bipolar junction transistor (BJT) and a sensing/vertical BJT and can be used as a biosensor. The amplifying bipolar junction transistor (BJT) is horizontally disposed on a substrate. The amplifying BJT has a horizontal emitter, a horizontal base, a horizontal collector, and a common extrinsic base/collector. The common extrinsic base/collector is an extrinsic base for the amplifying BJT. The sensing BJT has a vertical orientation with respect to the amplifying BJT. The sensing BJT has a vertical emitter, a vertical base, an extrinsic vertical base, and the common extrinsic base/collector (in common with the amplifying BJT). The common extrinsic base/collector acts as the sensing BJT collector. The extrinsic vertical base is separated into a left extrinsic vertical base and a right extrinsic vertical base giving the sensing BJT has two separated (dual) bases, a sensing base and a control base. The Darlington pair sensor has high in-situ signal amplification with low noise and uses substrate space effectively.

Darlington pair bipolar junction transistor sensor

A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

Direct growth of lateral III-V bipolar transistor on silicon substrate

A method of forming an electrical device that includes forming a multilayered fin composed of a first source/drain layer for a first transistor, a first channel layer for the first transistor, a common source/drain layer for the first transistor and a second transistor, a second channel layer for the second transistor and a second source/drain layer for the second transistor. A common spacer is formed on the common source/drain layer that separates a first opening to the first channel layer from a second opening to the second channel layer. Gate structures are then formed in the first and second openings.

Series connected stacked vertical transistors for high voltage applications

A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.

Vertical bipolar junction transistor with all-around extrinsic base and epitaxially graded intrinsic base

A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices

Semiconductor channel layers vertically aligned and stacked, separated by a work function metal and a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal directly contacts a vertical sidewall of each layer. A first set and a second set of semiconductor channel layers vertically aligned and stacked, separated by a work function metal, a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal between the first set and the second set directly contacts a sidewall of each layer. Forming an initial stack of alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked, forming a vertical opening creating a first stack of nanosheet layers and a second stack of nanosheet layers, and exposing vertical side surfaces of the alternating layers of both stacks.

Nanosheet transistor with body contact

A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices

A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

III-V lateral bipolar junction transistor on local facetted buried oxide layer

A sensor including a surface plasmon resonance detector with a reservoir for containing a liquid sample. The sensor further includes a sensing metallic film positioned within the reservoir so that at least a majority of a surface of the sensing metallic film is to be in contact with the liquid sample being housed within the reservoir. The sensory also includes a semiconductor device having a contact in electrical communication with the sensing metal containing film that is positioned within the reservoir. The semiconductor device measures the net charges of molecules within the liquid sample within a Debye length from the sensing metallic film.

Biosensors including surface resonance spectroscopy and semiconductor devices

A semiconductor structure may include a vertical field effect transistor, the vertical field effect transistor may include a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory below the vertical field effect transistor. The resistive random access memory may include an epitaxial oxide layer, a top electrode, and a bottom electrode. The top electrode, which may function as the bottom source drain of the vertical field effect transistor, may be in direct contact with the epitaxial channel of the vertical field effect transistor. The epitaxial oxide layer may separate the top electrode from the bottom electrode. The top source drain may be arranged between a dielectric material and the epitaxial channel. The dielectric material may be in direct contact with a top surface of the epitaxial channel. The epitaxial oxide layer may be composed of a rare earth oxide.

Resistive random access memory integrated under a vertical field effect transistor

A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of the fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.

Vertical transistor with body contact

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Yorktown Heights, NY, United States of America

Tak H Ning